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When writing testbenches, it is a routine to take the entity we want to test, replace the entity word with component and put this into the architecture of the tetsbench before begin. Then create signals with the same name as the ports in this design to be tested and then created a component instance where we do the port map and generic map.

It is not a lot of work but gets annoying when it has to be done over and over again, certainly a tool must exist that can generated this text automatically?

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  • \$\begingroup\$ A clever IDE/editor can do such things for you. You don't neey a component declaration if you use the entity syntax: myInstance : entity myLib.myEntity port map (...); \$\endgroup\$
    – Paebbels
    Feb 29 '16 at 20:39
  • \$\begingroup\$ I made one that uses pyparsing to do this for verilog. Could be modified for VHDL, but that would require creating a language definition for VHDL for pyparsing, presuming one doesn't exist already. \$\endgroup\$
    – alex.forencich
    Feb 29 '16 at 20:53
  • \$\begingroup\$ There's a verilog mode for emacs which allows you to use automatics to complete port lists and module instantiations. I modified the template mode for emacs to create a testbench template that uses the automatics. Obviously this doesn't solve your problem, but maybe there's a similar solution for VHDL. \$\endgroup\$
    – Doov
    Feb 29 '16 at 21:04
  • \$\begingroup\$ OK, I guess I will write my own in C++. Will make things less annoying. \$\endgroup\$
    – quantum231
    Feb 29 '16 at 23:55
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    \$\begingroup\$ Online VHDL Testbench Template Generator - beta. \$\endgroup\$
    – user8352
    Mar 1 '16 at 3:14
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Emacs with VHDL mode can do that: set the cursor inside a entity, choose 

VHDL-> Port -> Copy

then 

VHDL-> Port -> Paste as Testbench

generates a testbench architecture with entity, architecture, signals, instance, clock generator and stimuli process. The testbench look and feel can be defined in the vhdl mode options: 

| [-]-\ Group Vhdl Testbench
|     |--- Option Vhdl Testbench Entity Name
|     |--- Option Vhdl Testbench Architecture Name
|     |--- Option Vhdl Testbench Configuration Name
|     |--- Option Vhdl Testbench Dut Name
|     |--- Option Vhdl Testbench Include Header
|     |--- Option Vhdl Testbench Declarations
|     |--- Option Vhdl Testbench Statements
|     |--- Option Vhdl Testbench Initialize Signals
|     |--- Option Vhdl Testbench Include Library
|     |--- Option Vhdl Testbench Include Configuration
|     |--- Option Vhdl Testbench Create Files
|     |--- Option Vhdl Testbench Entity File Name
|     `--- Option Vhdl Testbench Architecture File Name
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  • \$\begingroup\$ For a preexisting testbench you can use "VHDL-> Port -> Copy" followed by "VHDL-> Port -> Paste as Signals", "VHDL-> Port -> Paste as Component", "VHDL-> Port -> Paste as instance" \$\endgroup\$
    – Lincoln
    May 22 '18 at 16:47
  • \$\begingroup\$ All of those commands available on the menu have keyboard shortcuts as well, making this quite convenient if used a lot. \$\endgroup\$
    – Lincoln
    May 22 '18 at 16:51
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I usually use this online tool

https://vhdl.lapinoo.net/testbench/

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