When writing testbenches, it is a routine to take the entity we want to test, replace the entity word with component and put this into the architecture of the tetsbench before begin. Then create signals with the same name as the ports in this design to be tested and then created a component instance where we do the port map and generic map.
It is not a lot of work but gets annoying when it has to be done over and over again, certainly a tool must exist that can generated this text automatically?
myInstance : entity myLib.myEntity port map (...);
\$\endgroup\$