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I've skimmed through several sparse articles online about hysteresis in a MOSFET's I-V characteristics. What I found was sparse, but some articles attribute uneven-ness in the gate structure, causing some charge to move slower.

As for my limited knowledge of Physics, it's still reasonable to think that pulling or pushing out charge carriers would instantaneously collapse/build-up electric field. Not only that, the current must have something similar to a "momentum", even though electrons have extremely low mass.

I really don't have the time to read through all these articles and even if I did, my Physics is lacking. So can anybody just summarize this for me, or point to a shortened article?

Has there been any design of a MOSFET Gate Driver that deals with this issue?

EDIT:

Perhaps what I should've said is "Hysteresis in MOSFET's response time" (or maybe this is still incorrect?). I don't know what's wrong with me tonight. I'm shifting my sleeping schedule, so I already feel groggy.

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  • \$\begingroup\$ Perhaps the term you're looking for is "phase shift" or "time delay". \$\endgroup\$ – Dave Tweed Mar 1 '16 at 12:22
  • \$\begingroup\$ Are you referring to asymmetric rise and fall times? \$\endgroup\$ – Peter Smith Mar 21 '18 at 13:26
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I have been studying/working with MOSFETs for 25 years and I've never heard/read about "hysteresis in a MOSFET's I-V characteristics". So in my opinion: it does not exist.

Maybe it exists on a theoretical level but in practice I have yet to see it before I believe it exists.

The only hysteresis that you would encounter regarding a MOSFET is the hysteresis that you add with the surrounding circuit.

Please link to one or more of the articles where you see this phenomenon mentioned so I can have a look myself.

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  • \$\begingroup\$ ieeexplore.ieee.org/xpl/…, www-mtl.mit.edu/researchgroups/hslee/j9.pdf. Few more even if you just Google it yourself. \$\endgroup\$ – kozner Mar 1 '16 at 8:39
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    \$\begingroup\$ OK, but that is not hysteresis in IV-curves ! It is charge trapping for large signal behaviour. The IV-curves are a static behaviour which you can measure at DC. This charge trapping is not related to that. \$\endgroup\$ – Bimpelrekkie Mar 1 '16 at 8:43
  • \$\begingroup\$ @kozner: While the first one is unreadable due to a paywall, the second one makes the same point as FakeMoustache: it is on the lab level with sub millivolt to some millivolt ranges and refers to the threshold voltage, not something you would ever need to consider since the static threshold will vary by much larger amounts anyways and you need to consider that in your design already. \$\endgroup\$ – PlasmaHH Mar 1 '16 at 8:45
  • \$\begingroup\$ Completely my mistake, read EDIT. \$\endgroup\$ – kozner Mar 1 '16 at 8:47
  • \$\begingroup\$ I've created devices with hysteresis by letting the well be weakly tied in a bulk process. In practice, this is bad of course, but it has some interesting properties if you want to add more chaos to your chaotic oscillator. \$\endgroup\$ – b degnan Mar 1 '16 at 21:35
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Vishay manufactured this FET. IR fabbed devices have similar performance. A Fairchild FTP3P20 performs as expected. enter image description here

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If you look at the curves from an IRF9510, they do not conform to the expected results. I found this out when I tried to use one for a linear application. P-CH MOSFETs from other manufacturers do not, in general, have the same behavior. In the image below, the gate voltage is offset by an external power supply to just below the threshold voltage.

What I do not know, is the effect that causes this behavior. If you have this info, please help me out.IRF9510 on Tek 576 Curve Tracer, gate V offset by external power supply

I have been told that IR developed these MOSFETs for switching applications only. The N-CH FETs do not behave this way.

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  • \$\begingroup\$ I've heard of that but I have no idea of the cause. Who manufactured this FET? \$\endgroup\$ – peufeu Mar 21 '18 at 12:36

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