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I'm new to this site so excuse me if my question is not normal or a bit silly. However I am having an odd situation where Vivado 2015.4 seems to be optimizing my code and removing parts of it which it deems is not useful.

Trying to keep things simple, I am reading an SPI port on an Artix-7 FPGA and filling 4 FIFOs after each other, i.e. when one is filled I read a memory location from the first FIFO and write it to the second FIFO, and so on. I created a flag 'data_available' which goes high when data is in the FIFO.

The odd thing is that whilst testing the FPGA by downloading the bitstream to verify that all write enables and full flags are working correctly; when the data_available flag is outputted, then the system works fine, when the data_available flag is not outputted then nothing appears, as if the whole code is removed due to the flag not being set as an output.

Can anyone identify why this is happening and how to solve it? Should this information not be available please excuse me since as I said I don't know the norm of this site. The code is a bit too long to post.

Thanks :)

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  • \$\begingroup\$ The FPGA is physically incapable of ignoring your code. It will be doing exactly what you programmed it to do. If that isn't what you want, then you haven't programmed it to do what you want. Check your code. Simulate it (you are simulating right?). Verify the RTL netlist. FPGA debugging 101. \$\endgroup\$ – Tom Carpenter Mar 1 '16 at 18:14
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    \$\begingroup\$ What happens when you simulate it? If I had to guess you didn't wire your modules together correctly. I'll bet it's getting optimized out because when you don't output data_available no outputs from the module are needed by other modules. \$\endgroup\$ – Doov Mar 1 '16 at 18:22
  • \$\begingroup\$ Simulation gives required results. I check the downloaded program through an oscilloscope against the simulation to verify its working as intended. What i'm doing is checking that all the full flags and enable signals are being performed. These signals appear only when the data_available flag is also outputted and disappear when I dont output the data_available flag. I know the FPGA will respond to what is programmed, however I am not sure if the programmer optimizes the VHDL, and removes code which it thinks is useless. \$\endgroup\$ – K.Galea Mar 1 '16 at 20:06
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What is happening is perfectly normal.

When you write in HDL you are... Describing hardware, either its behavior or its implementation.

If you do not set the flag as output, could you tell the difference between two fpgas, one having all the shift registers, the other one lacking them? No.

And you are so lucky to have a synthesizer smart enough to optimize away your useless (as in producing no visible effect from the outside) code.

I think you can force the code to be included, but that would be pointless since you would not have any way of testing it. Either you start simulating, which is a Very Good Thing\$^\text{TM}\$, or you keep the flag as an output and live with it.

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  • \$\begingroup\$ I understand what you are saying. I have worked on FPGAs in the past and have learnt that the best way is to implement bit by bit instead of relying heavily on simulation. That is what I am currently trying to do and hence omitting certain output signals. Is there a way that I can turn off code optimization? \$\endgroup\$ – K.Galea Mar 1 '16 at 20:16
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    \$\begingroup\$ Why would you say that simulating is not the best way? What I can guess is that you did not take your time in learning how to. Do it, it pays off. \$\endgroup\$ – Vladimir Cravero Mar 1 '16 at 20:26
  • \$\begingroup\$ I must admit I never delved into it greatly. I'm still undergoing my Electrical Engineering course at the moment :/ any suggestions for sites that tackle simulations would be greatly appreciated :) \$\endgroup\$ – K.Galea Mar 1 '16 at 20:59

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