I'm new to this site so excuse me if my question is not normal or a bit silly. However I am having an odd situation where Vivado 2015.4 seems to be optimizing my code and removing parts of it which it deems is not useful.
Trying to keep things simple, I am reading an SPI port on an Artix-7 FPGA and filling 4 FIFOs after each other, i.e. when one is filled I read a memory location from the first FIFO and write it to the second FIFO, and so on. I created a flag 'data_available' which goes high when data is in the FIFO.
The odd thing is that whilst testing the FPGA by downloading the bitstream to verify that all write enables and full flags are working correctly; when the data_available flag is outputted, then the system works fine, when the data_available flag is not outputted then nothing appears, as if the whole code is removed due to the flag not being set as an output.
Can anyone identify why this is happening and how to solve it? Should this information not be available please excuse me since as I said I don't know the norm of this site. The code is a bit too long to post.