I am simulating a basic sample and hold circuit in TI TINA. The op amp is TI TLV333. enter image description here

The parameters are:

Vin - 1Hz - DC:150mV - Amplitude:1.3mV

Switching frequency:100Hz

The following two plots show the simulations under different capacitor (C2) values.

(1st: 1mF; 2nd: 1uF) enter image description here

Can anyone why the ripple and oscillation occur when using smaller capacitance? Thank you.

  • \$\begingroup\$ Look for FETs with lower gate and Miller capacitances - alternatively stated as lower gate charge storage. They will have higher ON-resistance as both depend on device area. You have to make the right tradeoff for your application. Meantime, plug in an IRF540 or something for a laugh... \$\endgroup\$ – Brian Drummond Mar 2 '16 at 15:00

The transistor is like a capacitor. The charge is stored in the channel. As soon as the transistor is switched off, the charge leaves through drain and source. This phenomenon is called charge injection.

Another problem is capacitive coupling. Switching the transistor causes a current across the parasitic capacitances.

These effects can be seen as spikes and additional charge on the capacitor.

Apart from that you are driving your transistor with an ideal source, add some source impedance to make the simulation more realistic.

Another problem with your circuit is that you did not consider the effect of the body diode. I can't see it in your simulation but the problem is there. Most likely because you are sampling quite fast and the voltages across the diode are too small.

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  • \$\begingroup\$ But why the signal becomes better if a larger value capacitor is placed? Thanks. \$\endgroup\$ – ppendless Mar 2 '16 at 11:57
  • \$\begingroup\$ Because the injected current (charge, actually) stays the same, so the voltage across the capacitor gets smaller. \$\endgroup\$ – Mario Mar 2 '16 at 11:58
  • \$\begingroup\$ Could you tell me what kind of problems will occur due to the body diode of the MOSFET? Thanks \$\endgroup\$ – ppendless Mar 2 '16 at 12:17
  • \$\begingroup\$ @ppendless It will conduct for input voltages smaller than the voltage stored on the capacitor. \$\endgroup\$ – Mario Mar 2 '16 at 12:28

I'm guessing a little of the gate signal is getting coupled into the opamp. This could be due to stray capacitive coupling, possibly in part thru the transistor, or ground bounce caused when the gate capacitance is charged and discharged, or something else.

Low noise requires squeaky clean design. You don't even have a bypass cap across the opamp, so you're a long way from low noise design. Start with a good ground, thinking carefully where the power return currents are flowing, and keep them from causing offsets at different points of the signal ground net.

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  • \$\begingroup\$ Thanks for your reply. I do have put a 100nF capacitor between the power supply of the op amp and the ground. \$\endgroup\$ – ppendless Mar 2 '16 at 12:02
  • \$\begingroup\$ Pretty great simulator if it can simulate ground bounce and bypass caps from just that circuit. :) \$\endgroup\$ – pipe Mar 2 '16 at 12:02
  • \$\begingroup\$ @pipe: I forgot this was a simulation, not a real circuit. In that case look more closely at coupling thru the transistor. \$\endgroup\$ – Olin Lathrop Mar 2 '16 at 12:05

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