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So, I'm trying to diagnose a simulation issue with the IXTT20N50D in CircuitLab, and created a very simple transfer characteristic test jig to do so:

TEST OF IXTT20N50D MODEL

.MODEL IXTT20N50D NMOS
+ LEVEL=3
+ L=2.0000E-6
+ W=5.5000
+ KP=1.0446E-6
+ RS=1.0000E-3
+ RD=.22202
+ VTO=-.89028
+ RDS=20.000E6
+ TOX=2.0000E-6
+ CGSO=3.5684E-9
+ CGDO=37.622E-12
+ CBD=4.8729E-9
+ MJ=1.5000
+ PB=2.6055
+ RG=10.000E-3
+ IS=1.3714E-6
+ N=2.0283
+ RB=1.0000E-9
+ GAMMA=0
+ KAPPA=0

V1 1 0 DC 0
V2 2 0 DC 30
M1 2 1 0 0 IXTT20N50D

.DC V1 -3 4 0.1
.PLOT DC I(V2)

.END

This should replicate the transfer characteristic graph from the datasheet, right? Well...I 'run' it in ngspice and then plot the current through the drain voltage source (aka i(v2)), and get:

transfer characteristic plot from ngspice

What did I do wrong to get a transfer characteristic plot that is 6 orders of magnitude off from what the datasheet says it should be? Or am I simply reading the graph wrong?

Also, I get a warning from ngspice even with the simplified form of the model that was suggested in the comments (commenting out all but L W and VTO):

Warning: Model issue on line 3 : .model ixtt20n50d nmos l=2.0000e-6 w=5.5000 vto=-.89028 ...
  unrecognized parameter (l) - ignored
unrecognized parameter (w) - ignored

And the resulting graph (with L and W migrated to the M1 line, and W fixed to be the correct magnitude of 5.5E-6):

enter image description here

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  • \$\begingroup\$ I read the same thing. I'm not up with SPICE 3 since I use EKV, but delete everything but the minimum for a Level 1 model so the defaults are used. You just need W, L, VT0, and see if it gets closer. It might just be that there's a magnitude off in the model. \$\endgroup\$ – b degnan Mar 3 '16 at 0:25
  • \$\begingroup\$ The 6 order of magnitude difference between your W and L parameters might be related...although I'd expect this error (if it is an error) to go the other way (lead to very high currents rather than very low currents). \$\endgroup\$ – The Photon Mar 3 '16 at 0:39
  • \$\begingroup\$ Based on documentation here it looks like you are specifying a gate width of 5.5 meters. \$\endgroup\$ – The Photon Mar 3 '16 at 0:44
  • \$\begingroup\$ Just can't resist sharing my little triumph reproducing this in LTSpice: i.imgur.com/zm7jhQr.png \$\endgroup\$ – feetwet Mar 6 '16 at 22:26
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Indeed, the gate width is 5.5 meters. Apparently somebody just twiddled the knobs to get the outcomes he wanted (measured). With l and w on the device instantiation line the current is 34A @ 4V.

Test of IXTT20N50D model

.model ixtt20n50d nmos (
+ level=3
+ kp=1.0446u
+ rs=1.0000m
+ rd=.22202
+ vto=-.89028
+ tox=2.0000u
+ cgso=3.5684n
+ cgdo=37.622p
+ cbd=4.8729n
+ mj=1.5000
+ pb=2.6055
+ is=1.3714u
* + l=2.0000u
* + w=5.5000
* + rds=20.000MEG
* + rg=10.000m
* + n=2.0283
* + rb=1.0000n
+ gamma=0
+ kappa=0 )

v1 1 0 DC=0
v2 2 0 DC=30
m1 2 1 0 0 ixtt20n50d l=2u w=5.5

.dc v1 -3 4 0.1

.control
  listing e
  run
  plot i(v2)
  write bug60.raw
  *quit
.endc

.end

enter image description here

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  • \$\begingroup\$ 5.5 meters! pretty much, if you don't have silicon, you cannot publish as you can make spice act however is convenient. of course, that's not true if you publish net lists, but people seldom do \$\endgroup\$ – b degnan Apr 30 '16 at 20:46

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