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I am trying to implement carry chain on FPGA and i want that resault from each block is written in register. Each block is 10 bit adder with following code:

-- Carry10 Adder-------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity CarryN is
    generic (DATA_WIDTH : natural := 10);

    port ( 
             cin    :in std_logic;
             cout   :out std_logic;
             Q :out signed ((DATA_WIDTH-1) downto 0);
             STOP :in std_logic

         );

end CarryN;

architecture rtl of CarryN is

--SIGNAL Q: signed ((DATA_WIDTH-1) downto 0);
SIGNAL pomocni: signed ((DATA_WIDTH-1) downto 0);
SIGNAL a : signed ((DATA_WIDTH-1) downto 0);
SIGNAL b    : signed ((DATA_WIDTH-1) downto 0);

begin

a<=(others => '0');
b<=(others => '1');

process (STOP,cin)
    variable s : signed ((DATA_WIDTH) downto 0);
    begin
    s := ('0' & a) + ('0' & b) + ('0' & cin);
    --resoult<=s((DATA_WIDTH-1) downto 0);
    cout <= s(DATA_WIDTH);
    pomocni<=s((DATA_WIDTH-1) downto 0);

    if (rising_edge(STOP)) then
    Q<=pomocni;
    end if;



    end process;

end rtl;

---------------------------------------------------------

So when i compile this code as TOP-LEVEL entity everything is fine and i get what i wanted. After that i have made TOP-LEVEL entity in which i use this 10bit adder as component for carry chain as fallows:

-- TOP LEVEL ENTITY-----------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Pokusaj is

    generic (DATA_WIDTH : natural := 10;
                N: integer :=100);

    port ( 
             clk1   :in std_logic;
             clk2   :in std_logic

         );

end Pokusaj;

architecture rtl of Pokusaj is


component CarryN    is
port ( 
             cin    :in std_logic;
             cout   :out std_logic;
             Q :out signed ((DATA_WIDTH-1) downto 0);
             STOP :in std_logic

         );

end component;


SIGNAL START: std_logic;
SIGNAL STOP: std_logic;
SIGNAL S: signed (200 downto 0);
SIGNAL reg: signed (1500 downto 0);
SIGNAL I: integer := 0;
--SIGNAL : signed ((DATA_WIDTH-1) downto 0);
--SIGNAL a : signed ((DATA_WIDTH-1) downto 0);
--SIGNAL b  : signed ((DATA_WIDTH-1) downto 0);

begin

START<=clk1 xor clk2;
STOP <=clk1 and clk2;

S(0)<=START;

 G_1 : for I in 0 to N-1 generate     

            BEGIN

            Delay_Element1: CarryN
           port map

            (S(I),S(I+1),reg (10*(I+1)-1 downto 10*I), STOP);

         end generate;


end rtl;
----------------------------------------------------------------

After that i get error that i have no clocks defined in design, but clock is defined fine in component CarryN. I have read about problems when compiler makes conclusion that clock is not necessary so he left it from design, but i can not figure out how can that be problem if i tested my component and everything works fine from it's prospective.

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  • \$\begingroup\$ Please post the concrete error message. And your creation of the clock may not be supported by Quartus. \$\endgroup\$ – Martin Zabel Mar 12 '16 at 15:45
1
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Generally speaking FPGA synthesis tools do not let you use logic to generate an internal clock without requiring you to explicitly run it through a clock buffer. You may also have to declare the net as a clock in the constraints file, as well as giving it specific timing values.

Modern FPGAs are highly optimized physically, with separate low-skew distribution "trees" for clocks, and highly configurable networks and switches for logic signals. They don't allow you to mix them except under carefully controlled circumstances — the clock input of any FF can only connect to a clock tree, and all of the other inputs can only connect to logic nets.

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