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When designing decoupling capacitors why there are always parallel capacitors arrangements with decreasing values? It seems a redundancy to have this kind of configuration because the equivalent circuit is just one insignificant increase in the single larger capacitor.
Take this circuit as an example: isn't it the same to put only one capacitor 1,100uF? And why does it use a 0.01uF? I mean, the first capacitor tolerance is probably larger than that!
Please some insight!
Short and sweet, it's because of the high-frequency ESR of the larger caps.
First, a storage capacitor (usually electrolytic & often with fairly significant ESR impeding its use to short high-frequency transkents/interferance to gnd) is often used to cushion demand fluctuation and low-frequency oscillations.
Next, a much smaller capacitor, usually a ceramic or tantalum with much lower high-frequency ESR, is used to help filter emi/rfi & transients.
Finally, most chips require a decouplic cap right next to the chip for cusioning the instantaneous load fluctuations of the high-speed chip. This is to overcome supply voltage fluctuations to the chip due to inductance in the power traces leading to the chip.
IMPORTANT NOTE:
When using a storage cap/filter cap pair, it is usually reccommendable to avoid using capacitor pairings where one is a multiple of the other. This is intended to reduce the chance of the capacitors, along with inductance/resistance from traces, creating a resonant circuit where the smaller cap can oscillate at a harmonic of the larger cap's resonating frequency.
