When designing decoupling capacitors why there are always parallel capacitors arrangements with decreasing values? It seems a redundancy to have this kind of configuration because the equivalent circuit is just one insignificant increase in the single larger capacitor. enter image description here

Take this circuit as an example: isn't it the same to put only one capacitor 1,100uF? And why does it use a 0.01uF? I mean, the first capacitor tolerance is probably larger than that!

Please some insight!

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    \$\begingroup\$ No because a larger-valued capacitor is physically larger and so has larger parasitic resistance and inductance. At high frequencies it is really less about the particular capacitance and much more the parasitics. There are many questions about decoupling on this site so I suspect yours is a duplicate of one of those. \$\endgroup\$ Mar 3, 2016 at 23:41
  • \$\begingroup\$ @OleksandrR. Tks! I'm afraid I couldn't find any similar question around... \$\endgroup\$
    – PDuarte
    Mar 4, 2016 at 0:38
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    \$\begingroup\$ Have a look at the site-suggested related questions. The top suggestion is particularly good. It's this one. \$\endgroup\$ Mar 4, 2016 at 1:53
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    \$\begingroup\$ Murata's application manual on decoupling is an excellent resource on this topic. \$\endgroup\$
    – The Photon
    Mar 4, 2016 at 4:06
  • \$\begingroup\$ That's a very good documentation \$\endgroup\$
    – PDuarte
    Mar 4, 2016 at 9:16

1 Answer 1


Short and sweet, it's because of the high-frequency ESR of the larger caps.

First, a storage capacitor (usually electrolytic & often with fairly significant ESR impeding its use to short high-frequency transkents/interferance to gnd) is often used to cushion demand fluctuation and low-frequency oscillations.

Next, a much smaller capacitor, usually a ceramic or tantalum with much lower high-frequency ESR, is used to help filter emi/rfi & transients.

Finally, most chips require a decouplic cap right next to the chip for cusioning the instantaneous load fluctuations of the high-speed chip. This is to overcome supply voltage fluctuations to the chip due to inductance in the power traces leading to the chip.

When using a storage cap/filter cap pair, it is usually reccommendable to avoid using capacitor pairings where one is a multiple of the other. This is intended to reduce the chance of the capacitors, along with inductance/resistance from traces, creating a resonant circuit where the smaller cap can oscillate at a harmonic of the larger cap's resonating frequency.

  • \$\begingroup\$ Could you elaborate on the "one is a multiple of the other" ? A 1uF capacitor is a multiple of a 260uF capacitor by a multiple of 260. I'm assuming this combination is OK but what are the guide lines. \$\endgroup\$
    – vini_i
    Mar 4, 2016 at 0:02
  • \$\begingroup\$ While you are correct, at least in that instance it's a very large multiple. At the worst case, obviously you're asking for trouble if you use, say a 1uF and a 0.5uF cap, probably not great to use a 1uF with an 0.1uF either, but once your multiple gets over, say 50, the effect should become mostly inconsequential (except in very sensitive circuits). - In the end, if you can avoid integer-divisible values, do...but if not, at least make sure to avoid single-digit integer divisible values. \$\endgroup\$ Mar 4, 2016 at 3:39
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    \$\begingroup\$ @RobhercKV5ROB, I've never heard the advice to avoid integer multiples of capacitor values. But I've definitely heard not to have too big a multiple between capacitors placed in parallel, due to anti-resonance that can occur. More detail in Neutrino's answer here. This effect does not depend on there being an integer multiplier between the two capacitor values, and it tends to get worse when there is a bigger difference in their values. To avoid this effect, choosing a large multiple between the two capacitors is entirely the wrong thing. \$\endgroup\$
    – The Photon
    Mar 4, 2016 at 4:02
  • \$\begingroup\$ @ThePhoton I can't find it right now, but I picked up that advice from a few references while working on some homebrew HAM receiver designs. It may be less problematic in less oscillation-sensitive circuits, but all my sources that mentioned decoup/bypass/storage cap sizing recommended against using low-integer multiples. Instead, they recommended using non-integer multiples wherever possible, and often would include 3-5 storage/bypass caps (often with resistors between/after) on a VCC-in connection to attempt to provide best possible short-to-ground for wideband noise. \$\endgroup\$ Mar 4, 2016 at 5:47

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