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I have an FPGA design that works ok in the lab, but timing analysis warns of some serious negative setup slack at worst case temperature and voltage.

I'm curious, what might the derating be? It's not in the datasheet. I found some tables online that suggest up to 40% at worst case temp/voltage, but for an unlisted process. The device we have targeted is on the 28nm process.

Does anyone have any experience or know how sensitive the timing is to voltage/temperature? particularly for 28nm?

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How the graph routing tools look at things is a delay number for length of the tree. If you are in 5% (arbitrary value) of the maximum, it throws a warning. Save your design output, and recompile it. You might find that the heuristic nature of routing graphs will cause you to have a better topology for that random seed of the day.

On the hardware side of things, at 28nm on a commercial process, I measured +-10% threshold difference over 10k gates. This is actually not a huge sample size, but it's enough to tell you that the "P" part of PVT is very real. You are in above threshold, so T doesn't matter that much outside of the fact that you will get heat islands that will cause higher impact ionization probability that will then cause localized charge injection and a localized shift in threshold, that then will cause your threshold voltage to become more negative. If you are worried about PVT, just burn some cells and make copies of your most active cells and toggle between them. That way you'll have a cycle to cool off.

If you are using Xilinx, I believe that they use TSMC's 28nm process and you can get all of the nasty process information from the IEMD proceedings.

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