I am trying to design an H-bridge inverter to supply maximum current to my coils. I need to supply as much current as possible so that I can make a electromagnet whose polarity constantly flips so that i can levitate a moving Halbach array over top of those coils.

I've tried a number of things to make my mosfets as efficient as possible but when I enter in my Rds values into PSIM the current drops to 4mA. I have a DC power supply capable of outputting 18V and 10A.

H-Bridge Circuit, All pull up and pull down resistors are at 1K ohms, coil resistance is at 0.85ohm, coil inductance is 3.25mH, Rds for the top two P channels is 0.07ohms @ 10V and the N channels have a 0.027 ohm resistance at 10V as well

when I run the simulation I get that the current is through the coil is only 4mA which is nowhere near enough, I'm not sure if I am simulating something incorrectly or if thats correct based on the way the circuit is designed. Does anyone know how to maximize the current the coil? also even with the RC snubber circuit my MOSFETS are heating up alot! is there a better way to reduce that? My PWM frequency is at 120Hz from an arduino, and its a 40% duty cycle.

My coils have 220 turns and are 18 gauge wire, with a radius of 2cm and a length of 2.5cm, they are air coils I dont have any core.

My mosfets are FQP27P06 FQP30N06L

Thanks in Advance

EDIT After fixing the orientation of the PMOS my output looks good. enter image description here

However I'm finding that the magnetic field produced through these coils is not strong enough to levitate my pod. Is there something I can do to make this stronger?



simulate this circuit – Schematic created using CircuitLab

  • 2
    \$\begingroup\$ Well first off it looks like you have your P-Channel upper MOSFETs inserted into the simulation circuit with the source and drain interchanged from what they should be. Notice how the body diode is oriented so as to be always forward biased in the circuit. \$\endgroup\$ Mar 4, 2016 at 3:47
  • \$\begingroup\$ What inductance and resistance does the coil have in your simulation? \$\endgroup\$ Mar 4, 2016 at 4:14
  • \$\begingroup\$ @MichaelKaras ahhh didn't notice that was flipped, thank you for pointing that out. I will update the post with the new results \$\endgroup\$
    – Jawzie
    Mar 4, 2016 at 4:36
  • \$\begingroup\$ @BruceAbbott My inductance is set to 3.25mH that I calculated using an online calculator, and the resistor is 0.85ohms which is also from an online calculator. \$\endgroup\$
    – Jawzie
    Mar 4, 2016 at 4:38
  • 1
    \$\begingroup\$ After you fix the PMOS orientation, make sure to post what mosfets you're using. 18V is fairly high and likely to come close to exceeding the Vgs limit of most actual mosfets. \$\endgroup\$
    – Dave
    Mar 4, 2016 at 5:58

1 Answer 1


The charge-discharge voltage of the gate, is between the gate-source of the MOSFET.

You need to drive the gate of the P-MOSFET to the source voltage that, in your case is 18V to turn it off.

As you say, you are getting near 5V at the gate, so the P-MOSFETS are always conducting, and the N-MOSFETS are switching.

You are basically shorting the bridge at the PWM frequency and duty-cycle. To confirm, measure the current consumption, even with a low output current it should be high.


  • ATMega outputs are not meant to be used at these potential (voltage).
  • You don't include a resistor between the output of the ATMega and the gate, it is probably driving more current than it should.
  • The resistors on the leg form a voltage divider. Without drive signal, the voltage will be near \$vcc/2\$, the two transistors in one leg will conduce.

This is just a sketch

enter image description here

With this circuit the P-MOSFET gate-source will be 0V (thought pull-up resistor) and it will be non-conducting. When the NPN transistor is conducting it will pull the P-MOSFET gate-source to a low voltage (you can change the pull-down resistor to adjust this voltage).

  • \$\begingroup\$ Yes. This circuit is better. But on the off chance that you can't drive the mosfets hard enough and they still get hot from being in the linear region too long, consider adding a BJT buffer circuit. It's an NPN on top of a PNP, with the bases tied together for the input and the emitters tied together for the output. Those buffers should be driving the mosfets and should be between the mosfets and the logic shifting Q1 transistor. \$\endgroup\$
    – Dave
    Mar 6, 2016 at 1:53
  • \$\begingroup\$ Yes, it's just a sketch. The drive circuit is of choice of the user (totem pole, pulse transformer, integrated drive, opto isolated). The question is that the P-MOSFET source is at the supply rail, so with 0V at output of the ATMega the vgs will be 18V, and with 5V the vgs is 18-5V, sufficient to turn near fully on, so there's no off state of the P-MOSFETS on the original schematic. \$\endgroup\$ Mar 6, 2016 at 2:04

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