I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "cin" goes high, signal starts to propagate through chain and in moment when STOP occurs, propagation is sampled by registers. To do so, all it takes is to set all the bits of the first operand (input a) to ‘1’ and the bits of the second operand to ‘0’ (input b). Code which works fine for me is :
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity SignedCounter2 is generic ( DATA_WIDTH : natural := 10 ); port ( cout :out std_logic; izlaz: buffer signed ((DATA_WIDTH-1) downto 0); a: in signed ((DATA_WIDTH-1) downto 0) ; b: in signed ((DATA_WIDTH-1) downto 0) ; clk1: in std_logic; clk2: in std_logic; cin: in std_logic ); end SignedCounter2; architecture rtl of SignedCounter2 is SIGNAL reg: signed ((DATA_WIDTH-1) downto 0); SIGNAL buf: signed ((DATA_WIDTH-1) downto 0); SIGNAL STOP: std_logic; begin STOP<=clk1 and clk2; process (cin,clk1,STOP) variable s : signed ((DATA_WIDTH) downto 0); begin s := ('0' & a) + ('0' & b) + ('0' & cin); buf<=s((DATA_WIDTH-1) downto 0); cout <= s(DATA_WIDTH); if (rising_edge(STOP)) then izlaz<=buf((DATA_WIDTH-1) downto 0); end if; end process; end rtl;
With such structure of code i get exactly what i need; carry chain with fast paths as is show in next picture.
Cell structure with fast lines:
Problem is that operands "a" and "b" need to be declared somehow else then input signals. When I try to declare them fore example as SIGNAL or CONSTANT carry line gets deformation (fast paths are not used or cells are placed at strange way).