I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "cin" goes high, signal starts to propagate through chain and in moment when STOP occurs, propagation is sampled by registers. To do so, all it takes is to set all the bits of the first operand (input a) to ‘1’ and the bits of the second operand to ‘0’ (input b). Code which works fine for me is :

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity SignedCounter2 is

    generic (

    DATA_WIDTH : natural := 10


    port (

             cout   :out std_logic;
             izlaz: buffer signed ((DATA_WIDTH-1) downto 0);
             a: in signed ((DATA_WIDTH-1) downto 0) ;
             b: in signed ((DATA_WIDTH-1) downto 0) ;
             clk1: in std_logic;
             clk2: in std_logic;
             cin: in std_logic


          end SignedCounter2;

architecture rtl of SignedCounter2 is

SIGNAL reg: signed ((DATA_WIDTH-1) downto 0);
SIGNAL buf: signed ((DATA_WIDTH-1) downto 0);
SIGNAL STOP: std_logic;


STOP<=clk1 and clk2;

process (cin,clk1,STOP)
    variable s : signed ((DATA_WIDTH) downto 0);
    s := ('0' & a) + ('0' & b) + ('0' & cin);
    buf<=s((DATA_WIDTH-1) downto 0);
    cout <= s(DATA_WIDTH);

    if (rising_edge(STOP)) then
        izlaz<=buf((DATA_WIDTH-1) downto 0);
    end if;

    end process;

end rtl;

With such structure of code i get exactly what i need; carry chain with fast paths as is show in next picture.

Internal structure of carry chain

Cell structure with fast lines:

Cell structure

Problem is that operands "a" and "b" need to be declared somehow else then input signals. When I try to declare them fore example as SIGNAL or CONSTANT carry line gets deformation (fast paths are not used or cells are placed at strange way).

  • \$\begingroup\$ I think you are really going to struggle to make this approach work, it's just not how the tools are designed to operate. They are designed under the assumption that you are building a synchronous logic system and all that matters is that the data has stabalised to the right value by the time the next clock edge hits. \$\endgroup\$ – Peter Green Mar 4 '16 at 18:02
  • \$\begingroup\$ I am sure about that, but I was searching a lot how to implement TDC on low cost FPGA such as Cyclone IV and for now I have found one scientific article that is talking about that; they have used this technique for creating delay lines. Link: thinkmind.org/download.php?articleid=sensorcomm_2015_2_20_10046 \$\endgroup\$ – Ivan Mar 4 '16 at 18:23

You need to convince the synthesizer that a and b can change at any time — if it believes that they are constants, it will optimize them away.

It doesn't matter how they can change. One simple way would be to have a shift register whose serial input comes from an external pin, and whose outputs drive a and b.

You can ground the pin externally, and then put logic (e.g., XOR gates) between the shift register and the adder to produce the bit patterns you actually want.

| improve this answer | |
  • \$\begingroup\$ Problem solved ! Another problem occurs when I try to add my entity "SignedCounter" as component in TOP LEVEL entity; no clocks defined in design ! So "SignedCounter" works fine as top level entity but when I try to involve this entity as component something goes wrong. \$\endgroup\$ – Ivan Mar 6 '16 at 18:27
  • \$\begingroup\$ @Ivan This is a different question and may be related to your other question. \$\endgroup\$ – Martin Zabel Mar 12 '16 at 16:41

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