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I'm still figuring out analog electronics with my waveform generator project. It has a 9V power supply that I split into +/-4.5V rails with an op amp virtual ground (the subject of an earlier question). The +4.5V side powers an ATmega328P that generates an 8-bit digital waveform on pins D0-D7. Those lines go through an R2R resistor network to generate an analog signal in the rough range of 0-4V. Then I use the negative power rail and an op amp to center the signal on the 0V virtual ground.

So it works, but the waveform is noisy as hell. I kind of expected this, but not this bad. It's not breadboard noise because it's soldered on a real prototype board. There is relatively little noise across the positive and negative rails, so I think the noise is mostly in the virtual ground. (I know that "ground" doesn't normally have noise, but this is a virtual ground and the "noise" is relative to a theoretical 0V point centered between the +4.5V and -4.5V rails.)

Noise in waveform

I measured the noise between the virtual ground and the +4.5V rail and used the FFT function of my oscilloscope to see if there were any dominant frequencies. I am not so good at reading this but nothing stands out.

enter image description here

I tried capacitors of different values across the virtual ground and +4.5V rail. A 10pF capacitor did nothing. But a 10uF capacitor reduced the noise dramatically!

enter image description here

The stairstepping is due to the 8-bit resolution of the waveform and my not having a capacitor to smooth it out. I know the frequency of the stairstepping and the frequency of the waveform, and knowing the resistance of the R2R network (10k) I was able to calculate that a 1nF capacitor would filter out the stairstepping, and it does.

But what I don't understand is, how do I calculate the value of the capacitor necessary to eliminate the virtual ground noise? I think I need a low-pass filter that just allows my waveform through. That's an RC filter, but what's R? Do I use the resistance of my load and use that to calculate C?

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  • \$\begingroup\$ R is the output impedance of the opamp driving your virtual ground, at the frequencies of interest - the noise frequencies. At low frequencies it'll be low (open-loop output Z / open-loop gain, assuming a unity gain opamp) but it'll rise as gain reduces with frequency. Link to opamp's datasheet for more help. Looking at your prev question, you may simply need to decouple the opamp input ... in which case R = (R1 and R2 in parallel). \$\endgroup\$ – Brian Drummond Mar 5 '16 at 16:36
  • \$\begingroup\$ Makes sense--enter as an answer so I can mark it correct. :-) \$\endgroup\$ – Willis Blackburn Mar 5 '16 at 16:39
  • \$\begingroup\$ It would be easier to help if you share your circuit schematic. Exactly what circuit did you use to create the virtual ground. That said, more capacitance between the power rails and the virtual ground is likely to reduce noise (until, if you are driving the virtual ground with an op-amp, the op-amp becomes unstable due to capacitive loading) \$\endgroup\$ – The Photon Mar 5 '16 at 16:39
  • \$\begingroup\$ It's the schematic from the earlier virtual ground question: electronics.stackexchange.com/questions/219951/… \$\endgroup\$ – Willis Blackburn Mar 6 '16 at 0:26
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R in the R-C filter is the output impedance of the opamp driving your virtual ground, at the frequencies of interest - the noise frequencies.

At low frequencies it'll be very low (open-loop output Z / open-loop gain, assuming the opamp is used as a unity gain buffer) but it'll rise as gain reduces with frequency. Link to opamp's datasheet for more help.

Looking at your previous question, you may simply need to decouple the opamp input ... in which case R is simply (R1 and R2 in parallel), where R1 and R2 are the voltage divider on the opamp input.

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  • \$\begingroup\$ The op amp is a TL071 (actually one quarter of a TL074). \$\endgroup\$ – Willis Blackburn Mar 6 '16 at 0:29
  • \$\begingroup\$ Data sheet: ti.com/lit/ds/symlink/tl072.pdf \$\endgroup\$ – Willis Blackburn Mar 6 '16 at 3:20
  • \$\begingroup\$ I looked at the FFT on a different horizontal scale and noticed a peak at 19.6kHz. Still plenty of noise elsewhere by the peak was noticeable. I couldn't find output impedance vs. frequency in the data sheet but if we assume that it's something like 50 then that with the 10uF cap would give a -3dB cutoff frequency of 318Hz, and the attenuation of 19.6kHz would be pretty good. The smaller caps I have here (10nF and such) would mostly leave low-kHz signals alone, so I suppose that's why I'm not seeing any effect. Any reason to think that 10uF is a bad choice? \$\endgroup\$ – Willis Blackburn Mar 6 '16 at 3:29
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A virtual ground is like a voltage source with a certain impedance. The size of the capacitor will depend on this impedance and the load you have on your virtual ground.

The noisy waveform looks like you have some switching activity that loads your virtual ground. For this reason it is better to consider the problem in the time domain. You need to figure out how large the current spikes are that are generated on your virtual ground and how much charge is transferred. Assuming a sharp spike all the charge has to be supplied by the capacitor and you will observe a voltage change of delta V = delta Q / C. The capacitor should be sized accordingly to limit this voltage drop/increase to fit your requirements. You should also be careful to place the capacitor close to the load in order to keep inductances low.

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  • \$\begingroup\$ Appreciate your answer, but I don't know how to figure out how large the current spikes are. \$\endgroup\$ – Willis Blackburn Mar 6 '16 at 3:31
  • \$\begingroup\$ It is not so easy unless you have good models of your components and you can do a computer simulation. However, for a small capacitor you should be able to get a good measurement of the spike. Increasing the capacitor by a factor of 10 should decrease the amplitude by the same amount. So it is not complete guesswork. \$\endgroup\$ – Mario Mar 6 '16 at 15:08

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