The problem as it turns out is down to your choice of names for modules. You must remember that the schematic is first converted to HDL before it is synthesised (the conversion is internal), which means that you must use valid HDL module names.
In fact the error message document page gives you a link to a list of valid name characters and tells you to "Rename the logic function using legal name characters"
The list of allowed characters from that link is dependant on what the name is being used for, but to cut a long story short, basically the following is a list of valid characters:
A-Z (Alphabet) characters are permitted
0-9 (Digit) characters are permitted, but only if they are not the first character
_ (Underscore) is allowed, but only if not the first or last characters (I think).
The following are invalid:
(Space) is not allowed under any circumstances anywhere. Spaces are evil!
+-*/\&()... (Symbols) Well basically any symbol except
In your design you had named the modules
4 bit Adder and
2Bit Adder. Both of these are invalid - they include spaces which are disallowed, and also have a digit as the first character which is also not allowed.
Valid options would be things like
Adder1Bit, and so on.
It would probably also be worth your while diving into an HDL language - Verilog or VHDL. Even basic knowledge of the language would make life far easier for you - schematic/graphical entry will only get you so far (there are some topics on EE.SE that compare the differences).
As an example, your full adder in Verilog would be:
module Adder1Bit (
assign halfSum = A ^ B; //A xor B
assign S = halfSum ^ Ci; //Make the full adder sum
assign Co = (halfSum & Ci) | (A & B); //Make the full adder carry
Off topic: your
2Bit Adder module is not a 2bit adder, it is a 1bit adder (a.k.a full adder).