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I am using QuartusII for designing a Four bit ripple carry adder. I keep getting this error:

Error (275022): Illegal bus range or name for logic function for instance "instMyAdder" of type 4 Bit Adder


My schematics are all correct, and you can verify yourself, and I am not using any buses, yet I still get this error. I have tried doing everything. I restarted, but I still get the same exact error.
Here are my schematics:
Full Adder Design:
enter image description here

4 Bit Adder Circuit:

enter image description here

2 Bit Adder Circuit enter image description here

I have done everything that I can to fix this problem, yet I still get the same exact error every single time. Altera suggests changing the names, but I'm not sure what that means:
enter image description here

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    \$\begingroup\$ If your lower schematic is called "1Bit Adder", then your upper schematic is calling for "2Bit Adder"s which don't exist. \$\endgroup\$ – WhatRoughBeast Mar 6 '16 at 3:26
  • \$\begingroup\$ @WhatRoughBeast it is a one bit full adder, but I named the schematics "2 bit Adder", but it doesn't matter. I fixed it for you. \$\endgroup\$ – Andy_A̷n̷d̷y̷ Mar 6 '16 at 3:52
  • \$\begingroup\$ I'm not a Quartus user, but I note that all the valid logic elements have instance names of the form instx, where x is numeric. Are you sure that "instmyAdder" rather than inst1 is a legal name? \$\endgroup\$ – WhatRoughBeast Mar 6 '16 at 4:22
  • \$\begingroup\$ @WhatRoughBeast, the name doesn't matter. You can choose any name that you want. \$\endgroup\$ – Andy_A̷n̷d̷y̷ Mar 6 '16 at 4:34
  • \$\begingroup\$ If you rename A[1] to A_1 or A1, does the issue go away? Also, you really should get into the habit of using zero indexing - 0 should be the first one. \$\endgroup\$ – Tom Carpenter Mar 6 '16 at 4:57
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The problem as it turns out is down to your choice of names for modules. You must remember that the schematic is first converted to HDL before it is synthesised (the conversion is internal), which means that you must use valid HDL module names.

In fact the error message document page gives you a link to a list of valid name characters and tells you to "Rename the logic function using legal name characters"

The list of allowed characters from that link is dependant on what the name is being used for, but to cut a long story short, basically the following is a list of valid characters:

  • a-z A-Z (Alphabet) characters are permitted
  • 0-9 (Digit) characters are permitted, but only if they are not the first character
  • _ (Underscore) is allowed, but only if not the first or last characters (I think).

The following are invalid:

  •  (Space) is not allowed under any circumstances anywhere. Spaces are evil!
  • +-*/\&()... (Symbols) Well basically any symbol except _.

In your design you had named the modules 4 bit Adder and 2Bit Adder. Both of these are invalid - they include spaces which are disallowed, and also have a digit as the first character which is also not allowed.

Valid options would be things like Adder4Bit, FourBitAdder, Adder1Bit, and so on.


It would probably also be worth your while diving into an HDL language - Verilog or VHDL. Even basic knowledge of the language would make life far easier for you - schematic/graphical entry will only get you so far (there are some topics on EE.SE that compare the differences).

As an example, your full adder in Verilog would be:

module Adder1Bit (
    input A,
    input B,
    input Cin,

    output S,
    output Co
);

assign halfSum = A ^ B; //A xor B

assign S = halfSum ^ Ci; //Make the full adder sum
assign Co = (halfSum & Ci) | (A & B); //Make the full adder carry

endmodule

Off topic: your 2Bit Adder module is not a 2bit adder, it is a 1bit adder (a.k.a full adder).

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