I have built this power supply and clock signal extractor exactly as shown:


I have double-checked this and the rest of the clock multiple times.

However, my clock runs twice as fast as it should (each second, it counts to 2 instead of to 1.)

After spending about 5 hours trying to figure out what I did wrong, I read an unrelated article about half-wave vs. full-wave rectification. I then realized that perhaps the problem is with the instructions.

Given that the bridge rectifier in the supplied diagram is full-wave, wouldn't the clock signal from this diagram actually be 120 hz and not (as labelled) 60 hz?

The specific rectifier used is Jameco part # 103018.

edit: said "unrelated post" mentioned above: http://www.dutchforce.com/~eforum/index.php?s=ce079f0f532f189320af403ffacb6866&showtopic=18061

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    \$\begingroup\$ It will be a 60Hz signal that will vary between Vf and Vr of the zener diode. I've used the circuit before, feeding it into a Schmitt trigger to square it up. Perhaps your clock is receiving phantom edges if you aren't using a Schmitt trigger buffer to clean it up. \$\endgroup\$ Mar 6, 2016 at 6:24

1 Answer 1


The circuit will work correctly to produce a 60Hz signal from the mains supply.

During the half cycle where the supply terminal used as the reference is positive, the output will follow the input waveform until it reaches the reverse voltage specification of the Zener diode (e.g. 5V for a 5V Zener) at which point the output will be clipped to this voltage until the supply terminal decreases below the zener threshold.

During the half cycle where the supply terminal is negative, diode in the bridge rectifier forming the ground reference will be reverse biased and you will end up with 0V at the output.

Basically while you are using a full-bridge rectifier for your supply rail, you are actually only using a half bridge rectifier for the clock reference signal. Below is a simulation of the circuit with irrelevant parts of the bridge rectifier removed (parts which are not in the current path for the reference signal).

Simulation of circuit showing the described behaviour

While this circuit will indeed produce a 60Hz clock signal (or 50Hz in some parts of the world), the edges will have a very slow rise time (depending on the supply voltage) which may cause some phantom clock edges, especially if there is any noise on the power supply rails.

Ideally the signal would then be fed into a Schmitt trigger which will square up the signal edges while also removing phantom clocks caused by noise using a hysteresis loop.

As to why your circuit is running at twice the frequency, it is impossible to do anything but speculate as the rest of the design has not been disclosed.

  • \$\begingroup\$ Thank you Tom. I built the rest of the design exactly as specified on HowStuffWorks. (Original link above, instructions are across several pages.) The only other pieces involved are some 7490 ICs, so there could indeed be noise. The reason I don't think the culprit is phantom edges is that, over time, the clock is very precise about being twice as fast. I have timed it for a few minutes at a stretch and it is always exactly twice as fast as it should be, to within half a second (which is a reasonable margin of error given the primitive stopwatch I'm using to compare and my own reaction time.) \$\endgroup\$
    – Jim Brown
    Mar 6, 2016 at 17:04
  • \$\begingroup\$ @JimBrown Hmm. Do you have access to an oscilloscope? If so it would be good to try measuring the frequencies at each stage of the 7490s. If you don't have a 'scope, do you have something like an Arduino? as you can make a simple frequency counter/logic analyser from that. \$\endgroup\$ Mar 6, 2016 at 17:15

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