2
\$\begingroup\$

In Verilog, what techniques can be use for mapping an address bus onto different memory modules. Typical case: a microprocessor core whose address space is mapped to various memory modules: RAM, ROM, video RAM etc...

I've seen two approaches to this:

  • mapping the data bus according to the selected address range.
  • using a chip select on the target memory modules and enabling the the appropriate one according to the address.

Are there other techniques?

My understanding is the for the chip select approach, the memory modules should put their address and data ports into a high impedance state to effectively disconnect themselves from the bus. Is this correct and is it possible to synthesize this?

\$\endgroup\$
1
\$\begingroup\$

Verilog can handle the chip select approach - the high impedance state is called Z.

However, whether synthesis can handle it depends on whether whatever you're trying to synthesize to has the necessary tristate drivers available, and whether the synthesis program knows how to use them.

Disconnecting inputs from the bus isn't necessary; just the outputs.

It worked this way back when I specialized in ASIC and FPGA logic simulation using Verilog.

Your mapping the address bus method isn't clear enough that I can say much on that.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.