In Verilog, what techniques can be use for mapping an address bus onto different memory modules. Typical case: a microprocessor core whose address space is mapped to various memory modules: RAM, ROM, video RAM etc...
I've seen two approaches to this:
- mapping the data bus according to the selected address range.
- using a chip select on the target memory modules and enabling the the appropriate one according to the address.
Are there other techniques?
My understanding is the for the chip select approach, the memory modules should put their address and data ports into a high impedance state to effectively disconnect themselves from the bus. Is this correct and is it possible to synthesize this?