# Why doesn't Class C modulator operate in saturation?

The following circuit is a class C (actually class B) amplifier used in AM modulator in my previous question.

According to the textbooks, the transistor is driven into saturation in this class. A practical design has an additional resistor in the base. However, the results of simulation shows that collector-Emitter voltage is always above 0.2v and the transistor never operates in saturation.

Why doesn't the transistor operate in saturation by inserting the resistor R6?

simulate this circuit – Schematic created using CircuitLab

EDIT:

Simulation with different time steps give different results. the question was asked based on timestep=0.1us.

Here is the results of time domain analysis with timestep=0.01us:

EDIT:

It's somehow confusing for me. The above plots are achieved with time step 0.01us with circuit lab (since I haven't a simulation program on my desktop). but the previous results (before edits) were obtained with time step 0.1us. I don't know which one is correct!

Time domain analysis with timestep=0.1us:

Also the base voltage is continuously decreasing.

I've also placed a FET instead of BJT. here is the result for collector voltage and collector current.

• You can see the working conditions changing cycle by tycle (especially in Vbe). I don't believe you're running the sim long enough to see steady state operation. Also, looking at Ic you have 6A spikes. To truly saturate during a 6A Ic spike you'd need 0.6A base current! (And I don't think you want to do that, the output waveform would be very rich in harmonic content).
– user16324
Mar 6, 2016 at 12:16
• You should also run an FFT and see how much distortion you're getting on your output waveform. I'm interested too, since quite a few of the sources on the internet say "saturation" but my RF professor said "saturation is slow, we try to keep it in forward active."
– Dave
Mar 6, 2016 at 12:17
• @BrianDrummond Actually in the analysis of this circuit the collector current is considered as an Impulse train! See:"Communication Circuits: Analysis and Design". Mar 6, 2016 at 16:31
• I asked for an FFT (Fast Fourier Transform) not an FET (Field Effect Transistor). The reason being that your over driven picture of the output wave form has clearly discernible distortion based around the recovery of the base-collector junction. I was just interested if this was a product of over-driving a BJT or if actually putting the BJT into saturation causes waveform distortions.
– Dave
Mar 6, 2016 at 23:59
• @Andyaka I don't actually remember! But 4 years ago I've simulated and implemented the circuit and it worked. I still don't know why the textbook says that the transistor is in saturation. Aug 4, 2020 at 17:22

Why doesn't Class C modulator operate in saturation?

Why doesn't the transistor operate in saturation by inserting the resistor R6?

Why should it? Saturation has never been known to be very useful even for digital circuits because it's slow (This is of course only referring to BJT based designs and not MOSFET designed circuit where we depend on Saturation). This is due the the internal workings of the BJT. The Collector-Base junction is the largest junction due the the doping levels. When you forward bias the Collector-Base junction, you get a smaller depletion zone, which happens to be a bad thing. What happens is that you get excess holes leaching into the Collector instead of the Emitter. These holes have an almost zero chance to get to the Collector metal junction due the the relatively large distance from the depletion area to the metal junction (on the order of several diffusion lengths). This means those holes will recombine and not exit. Likewise, most electrons must also combine in the base region because if they didn't you'd get a charge build up. This makes the base a poor controller of the current and it begins to lose it's effectiveness at controlling the current from the collector to the emitter. In fact, in proper saturation, all new current flowing through the emitter is provided solely by the base.

A little wordy, I know. However, you need to understand the physics of a device to explain why things happen. With that knowledge in mind, we can see that if the number of minority carriers and majority carriers is lowered through excessive recombination then that means it will take longer to get back to a level which is useful. This is shown in diodes all the time as "Reverse Recovery," and the same phenomenon is going on in the BJT. Now, for a BJT the "Reverse Recovery" is a little different and a little the same. The same physics is going on but for the opposite effects. The reverse recovery time is now the time it takes the base to become a useful current controller with Hfe > 50 instead of Hfe closer to 1-5 in saturation. This "C-B Reverse Recovery" time is now the deciding factor in turning off the device since that junction must re-establish itself to be in cut-off. When you combine this with what I said before about it being the largest junction in the BJT, you see why saturation means your device will slow down. It has to take more time in order to rebias the C-B junction into reverse bias again to turn off. Saturation causes a BJT to slow down, become less current efficient, become less power efficient, and have lower amplification. All bad.

I hope any of this made sense to you, and if it didn't, remember, it just quantum physics, electromagnetics, and semiconductor device physics. This stuff isn't easy and takes time to understand.

A segue of sorts to prove that you don't hit saturation*********************

I took the time to get a hold of some sim time with a computer that had MultiSim 13 and ran the simulations needed to verify my old Professor (or prove him wrong, we'd let the data speak).

This is the circuit that I simulated:

Here is what I got:

1. You need to let that sim run much longer to get a steady state result. Below is a picture showing that it didn't begin to even out until 15 milliseconds after simulation start.
2. I also found that changing the time step would in fact change your transient answer. I used a time step of 1e-007 seconds and 1e-009 seconds respectively.
3. And, because I wanted to be thorough, I made sure that this was a good amplifier and ran an FFT on the same segments of waveform shown above (so between 20ms and 20.1ms)

In conclusion: You can clearly see that the voltage on the base of the transistor is never higher than the voltage on the collector. Per definition, this means that the device can only operate in either the "Cut-off" region or in the "Forward Active" region. This has been an enthralling question and I hope this has satisfactorily answered your question. If you need any clarification, please ask and I'll see whether I can get a hold of more sim time to answer it (1e-009 time sims take a few minutes each so if you need more charts please understand if I only get 1e-007). If the question is on device physics, please ask it in a new question as those answers can get quite lengthy.

• Thank you for your complete and helpful answer. But your sinusoid voltage source is only 1v, with larger voltages (I applied 10vpp) the output will reach near 0. I've just tested it a few hours ago by implementing the circuit in my previous question (by forcing the base voltage to be a complete sinusoid using a series LC resonant circuit!). Mar 7, 2016 at 16:56
• @SMA.D, and how bad was your THD? Also 10Vpkpk input with any bias less than +4V should blow your transistor quite nicely in the real world. You know they have limits right (Vebo = 6V max)? This series of questions that you've been asking has done nothing but confirm my opinion that you still need to learn the basics before doing any further design work.
– Dave
Mar 7, 2016 at 23:23
• I added a small resistor in emitter to prevent any possible harm to the transistor. but +/-5 volts (10 volts peak to peak) won't exceed 6V max (however the transistor gets a bit hot). I think THD is much more dependent on the Q of the resonator rather than any other factors. Mar 8, 2016 at 15:59
• "The operation of this circuit requires the collector-base junction of the transistor to become saturated (or to turn on) at the peak of every driving carrier cycle. The current pulse that flows as a result of this saturation has two effects. The direct effect in the output circuit is to cause the output tuned-circuit voltage amplitude to follow the variations in f (t). The indirect or reflected effect is to increase the loading in the base circuit, thus effectively causing the input driving voltage also to follow the variations in f(t)." Ref:Clarcke Mar 8, 2016 at 16:08
• @SMA.D, with a 5Vpk (10Vpkpk) signal. The transistor did go into saturation. The base reached down to -8.735V (so -2V below maximum allowed). The THD = 0.1722%, so that's higher. And the gain was -2V/V instead of the -5.8V/V from my sim where it didn't hit saturation. So far I've not seen any compelling evidence to tell me that I should operate the transistor in saturation. I'll run some more sims and see what I get for different variations of Q and input voltage and Saturation/non-saturation. However, all things held equal, the voltage input that drove the NPN to sat. produced worse results.
– Dave
Mar 8, 2016 at 17:27

Don't get hung up too much on the 0.2 V definition of saturation. Here's a section of the data sheet for a 2N3904: -

With a base current of 5 mA the table shows the saturation voltage to be 0.3 V. The other thing to consider with BJTs is that as you pump several mA into the base, the base-emitter voltage gets to a point where the collector-base region becomes forward biased and now the base is "lifting" the collector significantly above the "conventionally accepted" saturation voltage of 0.2 volts. Basically the BJT is not working in the conventional sense.

Looking at the characteristic curve of the 2N3904 you can see that saturation progressively rises as base current increases: -

I've shown a red circle on the graph at a collector current of about 12.5 mA - clearly, saturation is significantly above 0.5 volts and borderline 1V.

Don't get fixated on 0.2V!

• Thank you for answering. Do you mean that transistor is in saturation at some portions' of class C operation? Mar 6, 2016 at 11:34
• someone told me that this transistor is either in forward active or cut-off and it's never in saturation. Mar 6, 2016 at 11:36
• I'm saying that there isn't one particular voltage which is a true definition of saturation. I can't comment on your circuit because I don't understand the two plots you have - I would want to see base voltage, base current, collector voltage and collector current to get a handle on what your circuit is doing. Mar 6, 2016 at 11:37
• I've added some plots. Mar 6, 2016 at 11:46
• The top new graph clearly demonstrates that the colelctor voltage falls below 0V (due to the tuned circuit resonance) and back drives the base voltage. This circuit IS being significantly overdriven. Try lowering the base drive current. The 2nd graph shows amps of current into the collector and again - this circuit IS being driven beyond reasonable levels. Mar 6, 2016 at 11:56