Bits can be stored on any system that can latch, not necessarily a flip flop. For instance a latching mechanical relay can be used (and has been) or a magnetic core, etc. All the different technologies use different methods.
I'll deal with SRAM for now as it seems relevant to your previous question. Maybe add more later.
SRAM (static RAM) uses some kind of latch arrangement. The basic 6 transistor version uses cross coupled inverters:
This is a bit like the latch in the below diagram except there are no resistors (the collector resistors are replaced by the PMOS devices M2 and M4)
The value to be written is placed onto the BL lines, then the WL line is set and state is forced as M5 and M6 (which would connect at A1 and A2 - or E1/E2 as RB1 and RB2 are not present) have a much higher drive than M1,2,3,4, overriding them and forcing a state, which will then be held.
You can see this does not require a clock, just a simple set/reset operation. In contrast some latching circuits (there are many) use a clock to enable the set/reset to take place (effectively gating the input signal)
Here is a diagram of a gated latch:
Now you can see unless E is at 1 then S or R will have no effect. The clock could be attached to E to only enable changes to be latched when high.
DRAM (dynamic RAM) uses a capacitor to hold a charge which represents 1 or 0.
This requires a refresh to take place temporarily as otherwise the charge will leak from the capacitors. It is also generally slower than SRAM.
The advantage is that it can be made much smaller as it uses fewer transistors (check the average DRAM versus SRAM IC size/price and you can see a considerable difference)