I am trying to use the Memory controller Block in my Xilinx Spartan 6 FPGA to set up an interface with LPDDR memory. I read the MCB User guide, and I am quite clear about how it works, and how I would be able to use it. So, I generated a mcb controller using the Xilinx Core generator (using the MIG tool), but now I am stuck.
In the Spartan-6 FPGA Memory Interface solutions user guide (UG41) there is a constant reference to traffic generator. I am trying to understand what it is (this is a term I am hearing for the first time), but with no luck.
After 2 hours of googling, the closest answer I got was on this link. After a lot of guessing, I think traffic generator is an interface between the Memory Controller and the User logic, which defines how data is supposed to be exchanged between. But then it raises more questions :
- What exactly does it define?
- How do I define one on my own?
- Is it necessary for interfacing with the memory controller?
There is very little given about traffic generator in the user guide, and I am not able to find any answers. Any help is appreciated.