What is traffic generator (while using Xilinx Memory Interface Generator)

Question

I am trying to use the Memory controller Block in my Xilinx Spartan 6 FPGA to set up an interface with LPDDR memory. I read the MCB User guide, and I am quite clear about how it works, and how I would be able to use it. So, I generated a mcb controller using the Xilinx Core generator (using the MIG tool), but now I am stuck.

In the Spartan-6 FPGA Memory Interface solutions user guide (UG41) there is a constant reference to traffic generator. I am trying to understand what it is (this is a term I am hearing for the first time), but with no luck.

After 2 hours of googling, the closest answer I got was on this link. After a lot of guessing, I think traffic generator is an interface between the Memory Controller and the User logic, which defines how data is supposed to be exchanged between. But then it raises more questions :

• What exactly does it define?
• How do I define one on my own?
• Is it necessary for interfacing with the memory controller?

There is very little given about traffic generator in the user guide, and I am not able to find any answers. Any help is appreciated.

Answer 1

A traffic generator in this context is simply something that generates traffic on the memory interface.

It isn't a specific thing, it could be just a counter generating addresses and read and write signals, or test patterns to run memory tests, or random numbers.

In the context of a user design, it is simply that part of the overall design which uses the MIG interface - you could view the entire rest of your FPGA design as a Traffic Generator.

One way to define your own is to build a CPU based system that needs to access memory through the MIG interface.

As to being necessary; it's the other way around. If you don't have a Traffic Generator in your design, there is nothing that needs to access memory, so you don't need the MIG.