# Controlling the base of a N-Channel MOSFET on the high side of a circuit

With the help of some other members of the site, I was recently able to construct a gate driver circuit for some MOSFETs. I was operating N-channel MOSFETs on the "low side" of a circuit. Meaning that the source was tied to +0 VDC or ground of the circuit. I used an emitter-follower pair constructed from 2N3904 and 2N3906 bipolar junction transistors.

Assuming I want to build a circuit that switches an N-channel MOSFET on the high side of a circuit, I believe I can also use an emitter follower pair to control the gate of the MOSFET. The first obstacle is getting a voltage that is high enough to control the gate. Since the source of the MOSFET is at the supply voltage, I need a voltage that is higher than the supply voltage. For most MOSFETs, a Vgs of +10 VDC is sufficient. There are lots of ways to do this, in my schematic I'll just assume +10 VDC over the supply voltage is available.

The bases of the emitter-follower pair must be driven to voltage that is present on either of the collectors. So that means Vs or Vs + Vgs for an emitter-follower pair controlling a N-channel MOSFET on the high side.

Assume that my supply voltage is something high like + 100 VDC. I'll call this Vp for simplicity.

Any control signal I generate for the MOSFET will be at microcontroller logic and current levels. Either +5 VDC or +0 VDC at no more than 40 mA. Driving the bases of the emitter-follower pair with this signal would not produce the desired result. So, conversion of this logic level signal is necessary.

The easiest way to do this is to tie the bases of the emitter-follower pair to the gate-drive voltage via resistor. Then, another transistor can be used to pull the bases to low to toggle the state of the gate.

simulate this circuit – Schematic created using CircuitLab

The capacitor C1 is just for filtering

This circuit should result in the Vgs being +10 VDC or 0 VDC no matter the state of Q1 and Q2. However, the bases of Q1 and Q2 could wind up seeing a voltage difference equal to the supply voltage or greater when Q3 is driven into saturation by the clock. In particular Q1 would see a voltage difference of 110 VDC between the base and the collector. At the same time the base-emitter voltage of Q2 would wind up being 110 VDC due to the charge in the gate.

To prevent this I added R4. When the clock is low there is not enough current in R4 to matter. When the clock is high Q3 is saturated. The combination of R2 & R4 now form a voltage divider. This seemed to be the most obvious solution.

Questions

1. Is the voltage potential between the bases when Q3 is saturated even an issue? The resistor R1 would limit the current and the charge of the gate is not very large.

2. Does the presence of R4 limit the switching speed of the circuit?

3. Should I just replace the transistor Q3 with an optocoupler? The optocoupler would be tied to the collector of Q2 and the source of the N-channel MOSFET. What values on the spec sheet do I compare between my MOSFET and the optocoupler to make sure it is not the limiting factor?

Update 1

It seems like this circuit might be safer, but uses an additional PNP transistor. I'm unsure if R3 is necessary, but might reduce the total current needed by the circuit without affecting the performance.

simulate this circuit

• I'm sorry, I haven't reviewed your entire question (yet). But is there a reason that you don't want to simply use a P-channel MOSFET for the high-side switch? Commented Mar 8, 2016 at 18:11
• This will not work. You cannot turn off your load. When Q3 is on, the base voltage of Q1 will be about 88 volts., which will produce about 87 volts at the gate M1 via the Q1 base-emitter junction. For drain voltages less than about 83 volts the FET will be turned on, so the minimum load voltage will be about the same. Commented Mar 8, 2016 at 18:19
• @EricUrban If the MOSFET doesn't switch on instantly when its gate voltage rises the gate voltage will potentially exceed the specified max + 30 V and punch trough the oxide layer. This is a problem because the MOSFET doesn't switch on instantly after the gate voltage changes, there is a turn on delay of 18 ns + a current rise time of 55 ns during which Vgs can spike to 110 V. You should at least add a transient voltage suppressor from the gate to the drain.
– jms
Commented Mar 8, 2016 at 18:42
• @jms I agree with you. I think a bidirectional TVS diode on the gate is mandatory. Commented Mar 8, 2016 at 23:47
• Don't forget the flyback diode across the inductive load! Commented Mar 12, 2016 at 16:30

Is there a reason for not using a high side N channel MOSFET driver?

http://www.micrel.com/_PDF/MIC5019.pdf and a few more at http://www.linear.com/parametric/High_Side_Switches_*_MOSFET_Drivers

This solves the problem of driving the high side N fet without an additional mess of BJTs and with rocket sharp gate drive waveforms.

• I mostly build stuff from recycled junk. I usually don't find charge pumps. I did find a bunch of optoisolators I apparently salvaged. They might come in handy in this type of circuit. Commented Mar 12, 2016 at 23:52
• Ah. I didn't know that, sorry. Having endless resource of recycled junk and a lot of spare time is considered very special nowadays! Keep up the good work! Commented Mar 12, 2016 at 23:59

1) Is the voltage potential between the bases when Q3 is saturated even an issue?

The Q3 circuit is unsafe and too slow.

Please consider instead making Q3 into a current source; place a 1 kOhm resistor in series with the emitter. Then when CLK1 is high, the current through R2 is well defined (5 mA), regardless of supply voltage and of what the MOSFET is doing at the time. The gate drive will be a reliable copy of the square wave on CLK1. Since Q3 does not saturate, the circuit will be faster.

2) Does the presence of R4 limit the switching speed of the circuit?

Yes, of course. But the rest of the driver circuit is much slower, so I doubt that R4 at 10 Ohm makes any difference.

3) Should I just replace the transistor Q3 with an optocoupler?

That would have been ideal if the switching speed had been very low (< 1 kHz). At 10 KHz, no, not a standard opto-isolator. You'd need a high speed isolator (opto, capacitive or magnetic).

Also, if the duty cycle is never 100 %, consider a gate transformer.

• Thank for you the feedback. Are you commenting in reference to my second schematic? Do you have any links to literature on gate transformers? Commented Mar 12, 2016 at 17:11
• I Googled "gate transformers" and found a lot. coilcraft.com/prod_gatedrive.cfm productfinder.pulseeng.com/productList/POWER/… Commented Mar 12, 2016 at 17:33
• > Are you commenting in reference to my second schematic? // Both: neither schematic has a good solution for the driver. Use a current source instead. Commented Mar 12, 2016 at 17:47
• I don't actually understand what you mean by "current source" in this context. To me a battery or power supply is a current source. Commented Mar 12, 2016 at 18:09