With the help of some other members of the site, I was recently able to construct a gate driver circuit for some MOSFETs. I was operating N-channel MOSFETs on the "low side" of a circuit. Meaning that the source was tied to +0 VDC or ground of the circuit. I used an emitter-follower pair constructed from 2N3904 and 2N3906 bipolar junction transistors.
Assuming I want to build a circuit that switches an N-channel MOSFET on the high side of a circuit, I believe I can also use an emitter follower pair to control the gate of the MOSFET. The first obstacle is getting a voltage that is high enough to control the gate. Since the source of the MOSFET is at the supply voltage, I need a voltage that is higher than the supply voltage. For most MOSFETs, a Vgs of +10 VDC is sufficient. There are lots of ways to do this, in my schematic I'll just assume +10 VDC over the supply voltage is available.
The bases of the emitter-follower pair must be driven to voltage that is present on either of the collectors. So that means Vs or Vs + Vgs for an emitter-follower pair controlling a N-channel MOSFET on the high side.
Assume that my supply voltage is something high like + 100 VDC. I'll call this Vp for simplicity.
Any control signal I generate for the MOSFET will be at microcontroller logic and current levels. Either +5 VDC or +0 VDC at no more than 40 mA. Driving the bases of the emitter-follower pair with this signal would not produce the desired result. So, conversion of this logic level signal is necessary.
The easiest way to do this is to tie the bases of the emitter-follower pair to the gate-drive voltage via resistor. Then, another transistor can be used to pull the bases to low to toggle the state of the gate.
The capacitor C1 is just for filtering
This circuit should result in the Vgs being +10 VDC or 0 VDC no matter the state of Q1 and Q2. However, the bases of Q1 and Q2 could wind up seeing a voltage difference equal to the supply voltage or greater when Q3 is driven into saturation by the clock. In particular Q1 would see a voltage difference of 110 VDC between the base and the collector. At the same time the base-emitter voltage of Q2 would wind up being 110 VDC due to the charge in the gate.
To prevent this I added R4. When the clock is low there is not enough current in R4 to matter. When the clock is high Q3 is saturated. The combination of R2 & R4 now form a voltage divider. This seemed to be the most obvious solution.
Is the voltage potential between the bases when Q3 is saturated even an issue? The resistor R1 would limit the current and the charge of the gate is not very large.
Does the presence of R4 limit the switching speed of the circuit?
Should I just replace the transistor Q3 with an optocoupler? The optocoupler would be tied to the collector of Q2 and the source of the N-channel MOSFET. What values on the spec sheet do I compare between my MOSFET and the optocoupler to make sure it is not the limiting factor?
It seems like this circuit might be safer, but uses an additional PNP transistor. I'm unsure if R3 is necessary, but might reduce the total current needed by the circuit without affecting the performance.