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This is the all question.

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I thought that because Tcq>Th we will only count Tcq. If we need to know the minimum clock period, we should calculate the duration from the beginning to the output of DFF1. It makes TpdX+Tsu+Tcq+TpdA+TpdX+Tsu+Tcq = 51ns. Is that right?

I didn't get how the minimum clock period will occur when there are 2 flip flops. Because second flip flop depends on output of the first flip flop. Will we count Tcq twice?

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  • \$\begingroup\$ Where does it say that the minimum clock period will occur with 2 flip-flops? Or is "This is the all question" wrong? \$\endgroup\$ – WhatRoughBeast Mar 9 '16 at 20:03
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No. Your reference points are the rising edges of the clock signal. Everything starts and ends there.

Therefore, to calculate the minimum clock period, you start with the Tcq of any FF, add all of the logic delays leading to the input of any other FF (including itself), and add Tsu last. Use the maximum values of each delay for this calculation. In this circuit, there are three separate paths you need to consider.

Then, you go back and add up the minimum delay values (sometimes called "contamination delay" in modern texts) to verify that Th is also met on every FF.

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