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I would like to know how to replace an if statement with a case statement.

The if statement is

architecture super_mux_v1 of mux_case is
begin
    process (X,SEL) is
    begin
        if (SEL = "000") then
            Y <= X(0);
        elsif (SEL = "001") then
            Y <= X(1);
        elsif (SEL = "010") then
            Y <= X(2);
        elsif (SEL = "011") then
            Y <= X(3);
        elsif (SEL = "100") then
            Y <= X(4);
        elsif (SEL = "101") then
            Y <= X(5);
        elsif (SEL = "110") then
            Y <= X(6);
        else
            Y <= X(7);
        end if;
    end process;
end super_mux_v1;

My solution can be found below but I am getting some errors (case statement)

architecture super_mux_v1 of mux_case is
begin
    process (X,SEL) is
    begin
        case SEL is
        when "000" => Y <= X(0);
        when "001" => Y <= X(1);
        when "010" => Y <= X(2);
        when "011" => Y <= X(3);
        when "100" => Y <= X(4);
        when "101" => Y <= X(5);
        when "110" => Y <= X(6);
        end case;
    end process;
end super_mux_v1;

When I start compilation it comes up with an error saying

enter image description here

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  • 1
    \$\begingroup\$ I'm voting to close this question as off-topic because it belongs on SO \$\endgroup\$ – Scott Seidman Mar 10 '16 at 11:54
  • 3
    \$\begingroup\$ You forgot the when others => clause. Whether that is your problem is anybody's guess since you also forgot to tell us what the errors are. And you forgot to turn off CAPS LOCK too... \$\endgroup\$ – Brian Drummond Mar 10 '16 at 12:00
  • 5
    \$\begingroup\$ @ScottSeidman The question is bad, but on SO, really? VHDL? \$\endgroup\$ – pipe Mar 10 '16 at 12:03
  • 1
    \$\begingroup\$ user3880651, what is the line 37 with the error? Also check my answer - you should remove is from the process declaration \$\endgroup\$ – frarugi87 Mar 10 '16 at 15:57
  • 1
    \$\begingroup\$ @pipe Ya on Stack Overflow (tagged vhdl. Of course the question guidelines would want a Minimal, Complete, and Verifiable example - the declarations, X, Y, SEL presumably in an entity declaration). \$\endgroup\$ – user8352 Mar 10 '16 at 19:02
3
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Like the VHDL reference guide says (for instance here)

All possible choices must be included, unless the others clause is used as the last choice

In your if version you used it, since you wrote else .... In your switch one, however, you didn't.

Try writing

    case SEL is
    when "000" => Y <= X(0);
    when "001" => Y <= X(1);
    when "010" => Y <= X(2);
    when "011" => Y <= X(3);
    when "100" => Y <= X(4);
    when "101" => Y <= X(5);
    when "110" => Y <= X(6);
    when others => Y <= X(7);
    end case;

This should fix your problems

EDIT: There is another problem in your code: process (X,SEL) is should be process (X,SEL) (without is)

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  • \$\begingroup\$ Without seeing a declaration for X how do you know it has an element with an index value of 7? Now withdrawn, support for is was required in IEEE Std 1076.6-2004 (IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis, now withdrawn) 8.9.2 Process statement (but not -1999 same clause, noting is support was required in 8.4.5 Component declarations). It speaks to the age of the QuartusII synthesis tool. \$\endgroup\$ – user8352 Mar 10 '16 at 19:26
  • \$\begingroup\$ @user1155120 well, the OP said that the first example worked, so since he put X(7) in all the other cases I just copied it. As for the is, I couldn't understand if you are saying that it is needed or not ;) in every example I saw the is was missing.. \$\endgroup\$ – frarugi87 Mar 10 '16 at 21:29
  • \$\begingroup\$ is is optional in a process statement (and a component declaration). The question is whether or not the tool will accept it or not? \$\endgroup\$ – user8352 Mar 10 '16 at 23:22
  • \$\begingroup\$ @user1155120 thank you for your comment.. Yes, if the OP said what is the line giving that error it would be easier to fix... \$\endgroup\$ – frarugi87 Mar 11 '16 at 9:14
  • \$\begingroup\$ The particular VHDL analyzer won't specify any closer than the beginning of a statement for this syntax error. There's a historical presumption you provide valid VHDL code based on design flow. \$\endgroup\$ – user8352 Mar 11 '16 at 18:04

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