10
\$\begingroup\$

I'm trying to use a bidirectional port in Verilog so I can send and receive data through it. My problem is that when I try to assign a value to the port inside a task, I keep getting an error.

What is the correct way to assign a value to these types of variables?

My code is as follows:

    module test(value,var);

    inout value;
    output var;
    reg var,value;

    task sendValue;
      begin
        var = 1;
        value = 1;
      end
    endtask

   endmodule

and the error that I'm getting is:

Error: C:/[...]: (vlog-2110) Illegal reference to a net "value".

Thanks.

\$\endgroup\$

3 Answers 3

20
\$\begingroup\$

If you must use any port as inout, Here are few things to remember:

  1. You can't read and write inout port simultaneously, hence kept highZ for reading.
  2. inout port can NEVER be of type reg.
  3. There should be a condition at which it should be written. (data in mem should be written when Write = 1 and should be able to read when Write = 0).

For e.g. I'll write your code in following way.

module test (value, var);
  inout value;
  output reg var;

  assign value = (condition) ? <some value / expression> : 'bz;

  always @(<event>)
    var = value;

endmodule

BTW When var is of type wire, you can read it in following fashion:

assign var = (different condition than writing) ? value : [something else];

Hence as you can see there is no restriction how to read it but inout port MUST be written the way shown above.

I hope that explains it to you.

\$\endgroup\$
0
\$\begingroup\$

Check if the library you're using includes any tristate drivers - they're what I always used in this situation.

If you're forced to try to design your own tristate driver, remember that it's output must be Z whenever it should allow input instead.

\$\endgroup\$
0
\$\begingroup\$

Here my 2cents,

wire [32-1:0] DATA;//bidireccional port in VERILOG/VHDL
logic put_input_in_bidi;

assign m_sram_if.SRAM_DATA_READ = DATA;//read from inout port
assign DATA = (put_input_in_bidi==1'b1)? m_sram_if.SRAM_DATA_WRITE : 32'hZZZZ_ZZZZ;//write in bidi iout port
assign put_input_in_bidi =     (blabla == 0)  &&  (bobbob == 1);//control write in bidi using master information
\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.