I'm trying to use a bidirectional port in Verilog so I can send a receive data through it. My problem is that when I try to assign a value to the port inside a task, but I keep getting an error.
Which is the correct way to assign a value to these type of variables?
My code is the following:
module test(value,var); inout value; output var; reg var,value; task sendValue; begin var = 1; value = 1; end endtask endmodule
and the error that I'm getting is: ** Error: C:/[...]: (vlog-2110) Illegal reference to a net "value".