# How to assign value to bidirectional port in verilog?

I'm trying to use a bidirectional port in Verilog so I can send a receive data through it. My problem is that when I try to assign a value to the port inside a task, but I keep getting an error.

Which is the correct way to assign a value to these type of variables?

My code is the following:

    module test(value,var);

inout value;
output var;
reg var,value;

begin
var = 1;
value = 1;
end

endmodule


and the error that I'm getting is: ** Error: C:/[...]: (vlog-2110) Illegal reference to a net "value".

Thanks.

If you must use any port as inout, Here are few things to remember:

1. You can't read and write inout port simultaneously, hence kept highZ for reading.
2. inout port can NEVER be of type reg.
3. There should be a condition at which it should be written. (data in mem should be written when Write = 1 and should be able to read when Write = 0).

For e.g. I'll write your code in following way.

module test (value, var);
inout value;
output reg var;

assign value = (condition) ? <some value / expression> : 'bz;

always @(<event>)
var = value;

endmodule


BTW When var is of type wire, you can read it in following fashion:

assign var = (different condition than writing) ? value : [something else];


Hence as you can see there is no restriction how to read it but inout port MUST be written the way shown above.

I hope that explains it to you.

Check if the library you're using includes any tristate drivers - they're what I always used in this situation.

If you're forced to try to design your own tristate driver, remember that it's output must be Z whenever it should allow input instead.