# NMOS/PMOS logic vs. CMOS logic

With PMOS and NMOS, one can deduce that it is off, if

1. Vgs < Vt (NMOS) || Vsg < Vt (PMOS)
2. id = 0.

Now my question rests on the dependency of these conditions. I know proving condition 1 automatically implies condition 2. But can the same be said for the reverse?

Going off of this, in CMOS logic, does the current not matter in determining whether the mosfet is on or off? Clarifying the conditions of CMOS logic and how it is different from just PMOS/NMOS logic would be really helpful.

I'm assuming you would relate this to the most basic forms of CMOS logic, the inverter:

For the PMOS it is still common to also use $Vgs > Vt$ for the ON condition. But note that then the PMOS Vt would then be negative !

Condition 2 $Id = 0$ can also be achieved with both transistors OFF. So condition 2 does not always imply condition 1. But for the inverter powered with a sufficient Vdd (If Vdd = 0, that would also imply Id = 0) then either the NMOS or the PMOS transistor is ON (in a conductiong state). That is assuming Vin is either equal to 0 V or Vdd. (If Vin = roughly $Vdd/2$ then both transistors are conducting and Id would not be 0).

Id = 0 is not related to the state of the circuit. It is similar to the situation that a light switch can be ON or OFF, it does not mean a current has to flow. Removing the lightbulb (so no current can flow) does not prevent the switch from being in the ON or OFF position).

Likewise in an inverter depending on it's state either the NMOS or the PMOS is in a conducting state, that does not mean a current Id has to flow. This is the great benefit of CMOS logic, (almost) no current flows when the logic is in a static position.

• In your explanation, can you please include how this would affect the voltage drop of Vsd and Vds, given a current flow (Vin is accommodating) and with no current flow)?
– user91567
Mar 14, 2016 at 16:53
• Also, just to clarify, the condition that for sure indicates (in CMOS logic) that a mosfet is off is Vgs < |Vt| or Vsg < Vt. But in NMOS and PMOS logic, either Id = 0, or the aforementioned condition both prove that the mosfet is off right?
– user91567
Mar 14, 2016 at 18:18
• Stop thinking so much in conditions ! You're only confusing yourself. Both NMOS and PMOS need a Vgs of more than Vt for them to conduct. For logic Vin is either 0 (zero) or Vdd. Determine for both these cases what the Vgs of each transistor will be and if it will conduct or not. Hint: only one will conduct at any time. Then determine what the output voltage will be if the NMOS or the PMOS will conduct. Hint: Vout is either 0 (zero) or Vdd. Only after you fully comprehend this, only then will these conditions make sense. Mar 14, 2016 at 18:32
• To make things easier assume $Vdd = 5 Volt$ and $Vt = 1 Volt$ for both NMOS and PMOS meaning they conduct (between drain and source) when $Vgs > 1 Volt$ and when $Vgs < 1 Volt$ they do not conduct. That is a simplification but that does not matter at this moment. Mar 14, 2016 at 18:34
• Sorry, but this is where I'm slightly confused. What exactly denotes if it will conduct or not? Just the fact that Vov less than or greater than 0?
– user91567
Mar 14, 2016 at 18:41