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This question already has an answer here:

I am designing 4-layered PCB for the first time.

Searching web, I learned that normally we place layers in following way

TOP | GND | VCC | BOTTOM

Will there be problem if i place GND at the bottom? So that it works as below

TOP | VCC | BOT | GND

?

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marked as duplicate by Scott Seidman, Daniel Grillo, PeterJ, Ricardo, Neil_UK Mar 14 '16 at 12:48

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  • \$\begingroup\$ Do you have a design requirement or concern that would make you want the second? \$\endgroup\$ – Krunal Desai Mar 14 '16 at 6:49
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Well, it won't be "BOT" anymore :) (It would typically be known as MID or MID2).

In general, this should be alright. Keep in mind that it will make probing the signal layer considerably more difficult (you are limited to probing at vias).

Assuming a typical stackup where the middle planes are separated by a thick substrate, there really isn't much of a difference. You ought to have slightly better noise immunity and EMI shielding on the inner layer, though. You haven't specified what flavour of signals you are dealing with; as long as it's not too exotic, the effects of a change like this should be negligible.

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You could do that, but it doesn't make sense to me, unless you have some kind of weird application.

Doing Signal-Plane-Plane-Signal gives you:

  • Excellent high-frequency power delivery thanks to the capacitor formed from the two inner planes (think about it -- two large sheets of copper separated from each other by a thin dielectric)
  • Each signal layer has an immediately adjacent reference plane layer, making microstrip transmission line design easy, or more simply, return currents will enjoy a low impedance path barring any weird plane splits

What you've suggested will rob the first item, and create an interesting situation for the second where the stack up would dictate which of the two plane layers your signals will use as a reference plane (based on the distance to each).

You can always do a large flood pour of GND if you need it for some reason (thermal?) on the bottom layer, but unless you have a compelling reason, I'd stick with SPPS as the four layer stack up of choice.

I have read briefly about PSSP stackups, but I was not fully convinced by the few sentences that claimed improved EMI performance by burying all the signals inside; while it's true that solid plane layers would probably help in that regard, I personally don't think it'd be worth the routing hit -- you would have to via everything.

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    \$\begingroup\$ The first point, while true, are only true under certain conditions - The plane separation is kept small (I think < 15mils). If plane separation is large, then power delivery comes entirely from decoupling and not plane. \$\endgroup\$ – efox29 Mar 14 '16 at 7:00
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With 4 layers if you do have very fast edges, and you need need the inter-plane capacitance, this means you must have your 2nd and 3rd layer very close together (8-10mils) apart. If you are going with a standard 62mil thick pcb, this means your top and and bottom layer are very far from your reference planes. Everything is a compromise.

So what you can do is have Layer 1, 2, 3 close together. All your fast edges would be contained on the top layer, so that you have access to a reference plane and have the coveted inter-plane capacitance. Layer 4, would be treated as if it was a single layer board. You would need to run return path adjacent to each signal.

So you could have ground on the 4th layer if you choose too, but, it doesn't make sense too if you have a ground already in one of the mid layers.

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I've always found Henry Ott's techtips a valuable source of information.

Long story short: You loose the plance capacitance which is a very low inductive source of power. The faster your rise times are, the more you want that plance capacitance.

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