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I got surprised and to a degree shocked by finding that there is no proper established tool for designing and prototyping asynchronous circuits.

I keep searching using google and other means to find a good method to design VLSI asynchronous circuits, but so far the searches have failed to produce an answer.

There are some abandoned tools like Balsa, etc. for automating VLSI designs, but they are totally undocumented and hard to use. What I am looking for is something like FPGAs that we have in the synchronous world.

Anyway I appreciate it if you share the name of a reliable tool, and prototyping hardware that ease the burden of asynchronous circuit design.

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    \$\begingroup\$ You're not going to find it (commercial products and tools), because there's no market demand for it. Asynchronous design is much more difficult to get right, which is why it's more cost effective to limit its use to a few well-defined primitive functions (flip-flops, etc.) and then use synchronous techniques for all higher-level functions. Help us out by explaining your motivation for this and what you hope to accomplish. \$\endgroup\$
    – Dave Tweed
    Mar 14, 2016 at 13:09
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    \$\begingroup\$ The essence of a research project is to go something new, so the fact that there are abandoned dirt tracks instead of interstate highways is only to be expected. The only pointer I can suggest is to look for Teresa Meng's papers. I remember seeing one or two from ISSCC 1990 when it was held in Glasgow. \$\endgroup\$
    – user16324
    Mar 14, 2016 at 13:20
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    \$\begingroup\$ Similarly I studied with Simon Moore ( cl.cam.ac.uk/~swm11/resume ) who had a whole group working on this over a decade ago. I also was involved with an asynchronous hardware design tools startup .. which pivoted to synchronous low-power design tools, due to lack of market. Again you should look for papers from him and his research group. \$\endgroup\$
    – pjc50
    Mar 14, 2016 at 14:03
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    \$\begingroup\$ (Also, the people who are voting to close this question because it's not about electronics design are simply wrong) \$\endgroup\$
    – pjc50
    Mar 14, 2016 at 14:03
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    \$\begingroup\$ There's also NULL Convention Logic with a VHDL library of primitives. The primitive names indicate a link to Theseus Research Inc.. There was a NCL multiplier question on Stack Overflow withdrawn about the time I was going to do a testbench for it. (May 13, 2015). The idea shows up periodically for avoiding power analysis in cryptography (saw an IACR mention last week). A Book LOGICALLY DETERMINED DESIGN CLOCKLESS SYSTEM DESIGN WITH NULL CONVENTION LOGIC, Karl M. Fant. \$\endgroup\$
    – user8352
    Mar 14, 2016 at 19:17

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The Theseus logic NCL has been mentioned, there was also Handshake systems (Philips spin off) as well as Fulcrum Microsystems and Caltech. There was a asynchronous ARM processor called Amulet as well. And SUN Microsystems had a processor design team for this as well for a clockless SPARC.

I would call these clockless designs to avoid the confusion between logic design like ripple counters and these types of circuits. But in general either term is used.

DC (Design Compiler) from Synopsys as well Merlin from FTL systems also used to be available.

However, if you have a properly designed library of core cells this top level abstraction/description can become trivial. The core issue is that if you've designed a system that allows each cells to propagate forward a signal that says "result good" as well as propagating backwards "system available" the system self clocks and as such can be simply designed very much like software without concern for race conditions or timing for that matter.

So the tools used would be as simple as SPICE for cell level (transistor level) design and C for compiling into a set of primitives to be placed. For the life of me I can't find the C based tool (open source) that was used.

Look to people like Wesley Clark (He passed away recently) as well Ivan Sutherland and Karl Fant (mentioned elsewhere too).

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  • \$\begingroup\$ @Ehsan: It surely is interesting, but I fail to see how it addresses the question at all. Cell level layout is for ASIC design, not prototyping. \$\endgroup\$
    – Ben Voigt
    Jul 2, 2016 at 3:46
  • \$\begingroup\$ @Ben: I agree, and that is why I didn't accept his answer. But I could \emp{simulate} some basic asynchronous circuits using cell level libraries in MultiSim and LTSpice. NCL logic also has a sandbox Verilog library that one can prototype circuits based on NCL using FPGA : github.com/karlfant/NCL_sandbox. But I have not tried it yet. When I studied NCL I realized the huge overhead of the approach so I am trying to avoid it, and come up with something more practical. \$\endgroup\$ Jul 2, 2016 at 5:57
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If a register is clocked with a system clock, it would be considered synchronous. If that same register were clocked directly from a gate, logic circuit or generally anything besides a system clock it would be asynchronous. Altera's registers can be clocked from multiple system clocks, or by logic. You can build whatever type of gate circuitry you desire. . . It's been my experience with most kinds of ASICs or FPGAs that each time it is compiled, something is routed different. Thus propagation delays are always changing.

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An FPGA is the right hardware. But you won't be able to use the synchronous-focused synthesis software, because it makes the wrong transformations.

For example, an FPGA is perfectly capable of forming an oscillator built with an inverter chain. But if you define that inverter chain in e.g. VHDL and use one of the standard compilers, "NOT-gate pushback" will eliminate inverters pairwise and leave you with only one, and the device won't oscillate.

You may have to write some of your own synthesis software, which will be possible if you get enough information on the bitstream. I'd look into other research efforts that operate on the bitstream rather than the behavioral description -- things like glitch detection and reliability analyses are highly dependent on the mapping chosen by the synthesizer. Probably some work in the area of redundant fault-tolerant logic has already worked out some custom mapping techniques, since common product term elimination is one of the standard transformations performed by a traditional synthesizer, and absolutely destroys a redundant design.

When you control the usage of the FPGA logic element primitives such as lookup tables and local and global interconnect, you'll be able to use the inherent delays to realize your asynchronous design. Your optimization problem is a lot more difficult than fitting with the goal of meeting setup-and-hold times, but that's what makes it research.

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Depending upon the complexity of your circuit.. If your design is mostly digital, you might look at using Altera's Quartus system. Input your design with graphical and/or VHDL tools using asyncronously clocked registers or use just logic gates. Add dummy buffers, gates, signal pins etc.. as needed to delay signal paths to match whatever you need. (assuming your design is slower than their fastest CPLD gate delays <5 ns)

Many years of designing with their chips, I never found an errant simulator result. Smaller designs can be done with their free tools.

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  • \$\begingroup\$ "asyncronously clocked registers" ?! I am not sure if you got the concepts right. There is no such a thing as "asyncronously clocked registers". A circuit either has a clock (synchronous) or it doesn't (asynchronous). The tool I am looking for must support primitive Muller gate, dual-rail, 2NCL gates, etc. \$\endgroup\$ Mar 26, 2016 at 5:34

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