# Error when creating a task in separate file in verilog

module tb();

reg [7:0] a = 1;
reg [7:0] b;

initial begin
$display("%d", b); end task AddTask; input [7:0] a; output reg[7:0] b; begin b = a + 1; end endtask endmodule  The above code is compiled and simulated correctly; But I want to cut the task "AddTask" from the module "tb.v" and place it in a separate module "AddModule.v"(that is in a separate file) for clear coding. When I do this, modelsim can compile it but can't simulate it and give the error: " Unresolved reference to 'AddTask' ". Although I include AddModule.v, it can't recognize AddTask. Can you help me please, what's the wrong ? module tb; reg [7:0] a = 1; reg [7:0] b; include "AddModule.v" initial begin AddTask(a, b);$display("%d", b);
end
endmodule


module AddModule;

input [7:0] a;
output reg[7:0] b;

begin
b = a + 1;
end


• Where is Decrypt defined? Where do you reference it? This is not clear from your example code. – andrsmllr Mar 15 '16 at 8:21
• Sry It's AddTask, I'll edit this – Soheil Shababi Mar 15 '16 at 8:27
Try to declare only the task AddModule()` in a separate file without a surounding module declaration. This file can then be included within the scope of another module, e.g. within your testbench (as in your example code).