0
\$\begingroup\$
module tb();

    reg [7:0] a = 1;
    reg [7:0] b;

    initial begin
      AddTask(a, b);
      $display("%d", b);
    end

    task AddTask;

        input [7:0] a;
        output reg[7:0] b;

        begin
          b = a + 1;
        end

    endtask


endmodule

The above code is compiled and simulated correctly; But I want to cut the task "AddTask" from the module "tb.v" and place it in a separate module "AddModule.v"(that is in a separate file) for clear coding. When I do this, modelsim can compile it but can't simulate it and give the error: " Unresolved reference to 'AddTask' ". Although I include AddModule.v, it can't recognize AddTask. Can you help me please, what's the wrong ?

module tb;

    reg [7:0] a = 1;
    reg [7:0] b;

    `include "AddModule.v"

    initial begin
      AddTask(a, b);
      $display("%d", b);
    end
 endmodule

AddTask in a separate file:

module AddModule;

    task AddTask;

        input [7:0] a;
        output reg[7:0] b;

        begin
          b = a + 1;
        end

    endtask

endmodule 
\$\endgroup\$
  • \$\begingroup\$ Where is Decrypt defined? Where do you reference it? This is not clear from your example code. \$\endgroup\$ – andrsmllr Mar 15 '16 at 8:21
  • \$\begingroup\$ Sry It's AddTask, I'll edit this \$\endgroup\$ – Soheil Shababi Mar 15 '16 at 8:27
0
\$\begingroup\$

The problem is probably the nested module declaration. This is not allowed in Verilog, however is possible in SystemVerilog.
Try to declare only the task AddModule() in a separate file without a surounding module declaration. This file can then be included within the scope of another module, e.g. within your testbench (as in your example code).

\$\endgroup\$
  • \$\begingroup\$ Thank's a lot @damage, I declared only AddTask in a separated file 'AddTask.v' without any module declaration and it worked ! \$\endgroup\$ – Soheil Shababi Mar 15 '16 at 8:34
  • \$\begingroup\$ Also,when I synthesized it in Quartus, at first it didn't synthesize, but when I changed the postfix of files from .v (Verilog) to .sv (System Verilog), it synthesized correctly in Quartus as well as simulated in Modelsim ! \$\endgroup\$ – Soheil Shababi Mar 15 '16 at 9:05

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