# vhdl - convert a signal to integer

I have looked around on SE but couldn t find anything that worked properly for me.

I am looking for a way to convert a 4 bit signal_vector to an integer. However I do calculations on signals as well. This means I need the library called

use IEEE.std_logic_arith.all

This is (the condensed version of) what I have so far:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
USE ieee.numeric_std.ALL;
use IEEE.std_logic_unsigned.all;

signal counter: std_logic_vector(3 downto 0);

counter<=counter + "0001";
...

if ((to_integer(counter)) < (to_integer("0100"))) then

-- do something

end if;

this gives me the following error: Identifier "unsigned" is not directly visible.

• A better solution : signal counter : natural range 0 to 15; then counter <= counter + 1; if counter < 4 etc. In other words, say what you mean instead of making things more complicated.
– user16324
Commented Mar 15, 2016 at 13:02
• 1) I made a complete example of your code, but not get your error, but other ones. Can you please give a complete, but minimal example. 2) Do you need help on just the to_integerpart? Commented Mar 15, 2016 at 19:24

Please do not use the ieee.std_logic_arith library. It is outdated and makes problems when combining with others.

You can convert your signal as following:

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.ALL;

signal counter: std_logic_vector(4 downto 0);

counter<=std_logic_vector(unsigned(counter) + 1);
...

if (unsigned(counter) < to_unsigned(4, counter'length)) then

-- do something

end if;

If you plan to use a signal as a number most of the time, try to use type unsigned or signed if possible. You can always convert it to a std_logic_vector if needed.

EDIT:

I made a complete codesample that compiles and simulates in Vivado (should also work in modelsim):

library ieee;
use ieee.STD_LOGIC_1164.ALL;
use ieee.numeric_std.ALL;

entity test is
--  Port ( );
end test;

architecture Behavioral of test is
signal counter: std_logic_vector(4 downto 0) := (others => '0');
signal bigger: std_logic;
signal clk: std_logic;
begin

make_clk: process
begin
clk <= '0';
wait for 2 ns;
clk <= '1';
wait for 2 ns;
end process;

test: process(clk)
begin
if rising_edge(clk) then
counter<=std_logic_vector(unsigned(counter) + 1);
if (unsigned(counter) < to_unsigned(4, counter'length)) then
--do something
bigger <= '0';
else
bigger <= '1';
end if;
end if;
end process test;
end Behavioral;
• A few errors with this solution "no fesible entries to unsigned", unknown identifier "std_vector_logic", and No feasible entries for subprogram "TO_INTEGER". I don't know if this matters but I am using modelsim to code Commented Mar 15, 2016 at 12:25
• @trilolil That probably means you didn't delete ALL the non-standard libraries.
– user16324
Commented Mar 15, 2016 at 13:00
• (@trilolil - and haven't shown enough code to reproduce the problem.) The answer could show if unsigned(counter) < 4 then using package numeric_std or counter <= counter + 1; if counter < 4 then using package numeric_std_unsigned (-2008). Mind "At least one separator is required between an identifier or an abstract literal and an adjacent identifier or abstract literal." (2ns should be 2 ns, see IEEE Std 1076-2008 15.3 Lexical elements, separators, and delimiters, paragraph 4, Modelsim notwithstanding).
– user8352
Commented Mar 15, 2016 at 18:11
• @user1155120: Thank you, I corrected the 2 ns. Commented Mar 16, 2016 at 7:51
• In -2008 there's a bit literal lexical element with an integer length followed by a base specifier, 15.8). A physical literal is comprised of an abstract literal a separator and a unit name (not a lexical element, 5.2.4.1). 15.3 Lexical elements, separators, and delimiters "In some cases an explicit separator is required to separate adjacent lexical elements (namely when, without separation, interpretation as a single lexical element is possible)."
– user8352
Commented Mar 16, 2016 at 9:27