When i tried to code the below flip flop, the program failed. I'm using altera .

enter image description here

module DFF_SYNC_RESET(Din, nRst, Dout, Clk);
output Dout;
input nRst,Clk,Din;

wire D;
assign D= Din & nRst;

always@(posedge Clk)
  Dout<= D;


Can you please tell my failure in the code? enter image description here

Edit: After i encountered to another problem which is the same as in this page, the problem was solved


  • \$\begingroup\$ You should make D a wire and use a syntactically correct assignment likeassign D = Din & nRst;. \$\endgroup\$
    – andrsmllr
    Mar 15, 2016 at 13:19
  • \$\begingroup\$ thanks. I did but this time it threw these errors \$\endgroup\$ Mar 15, 2016 at 13:24
  • \$\begingroup\$ "DFF_SYNC_RESET cannot be declared more than once". You have more than one module with that name in your project \$\endgroup\$ Mar 15, 2016 at 13:33
  • \$\begingroup\$ this time it threw another error.left hand side of assignment must have a variable data type. thanks anyway, if the code seems okey, it is okey. i'll ask this to the lecturer \$\endgroup\$ Mar 15, 2016 at 13:45
  • \$\begingroup\$ @"DFF_SYNC_RESET cannot be declared more than once": Do you include this file in other files? The new error is quite clear, there is another module with the same name defined elsewhere in your design. \$\endgroup\$
    – andrsmllr
    Mar 15, 2016 at 15:57

1 Answer 1


In Verilog, if you assign to something in a procedural block (a block between begin and end), you need to make it a regsiter type. If you assign to something in a continual assignment (either an assign statement or the output of an instance of a module) you need to make it a wire type.

So you need to declare (You already edited this change into your question)

wire D;

on line 5, and

output reg Dout;

on line 2.

Also, D is somewhat superfluous. You could just have

output reg Dout
always @(posedge clk) begin
    Dout <= Din & nRst;

Even better, you should not use logic to simulate control features on flip-flops if your architecture makes full-featured flip-flops available. To code a DFF with syncronous reset for synthesis you would rather have

always @(posedge clk) begin
    if ~nRst 
         Dout <= 1'b0;
         Dout <= Din;

This will be more likely to use the built in features of the flip-flops in your architecture, resulting in faster and more resource-efficient implementation.

The error you showed doesn't seem to relate to how you defined your DFF_SYNC_RESET module. More likely it has to do with what files you are including in the synthesis or where you instantiated it, either in your testbench or in a higher-level module.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.