I'm designing a 56 bit shift register to store the bits coming in.
In my system, 8 bit data is keep coming in from a generator and I need to output the maximum value detected with 3 bytes either side of it.I want the data stored in a 56 bit wide shift register to give a out put that consists of the maximum and the other 7 bytes as shown in the graph.
The system compare each byte coming in with a temporary maximum value and it will give a 56 bit output each time when a new maximum value is detected.
I just wondering how can I keep the new coming in data at the centre so once the new-coming-in data is found to be greater than the temporary maximum I'm able to out put the whole 56-bit serial signal.
I tried to write something but Modelsim gave me this
Target type ieee.std_logic_1164.STD_LOGIC_VECTOR in signal assignment is different from expression type ieee.NUMERIC_STD.SIGNED. for temp_shift_register(31downto 24).....
shift : process (clk) begin if rising_edge(clk) and begin_req ='1' then for i in 55 downto 8 loop temp_shift_register(i) <= temp_shift_register(i-8); end loop; temp_shift_register(31 downto 24) <= temp_byte; else null; end if; end process;
The signal declarations are:
signal temp_shift_register : std_logic_vector (55 downto 0):= "00000000000000000000000000000000000000000000000000000000"; signal perm_shift_register : std_logic_vector (55 downto 0):= "00000000000000000000000000000000000000000000000000000000"; signal temp_byte : signed (7 downto 0);