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Is Nios II required when implementing UART core using the SOPC? (or a default Nios is included) I tried writing my own module for the uart connection but it didn't work out. I need a method to connect a sensor to the de2, any method is fine. If you guys could give a clear method about how can this be implemented
This link gives an idea what could be done but its not that clear
I need a idea on how to go about it. With so many manuals and softwares available for the Altera..
No, a NIOS II is not actually required when using IP components from QSys (the replacement for SoPC Builder), since you may always export the Avalon-MM bus which typically connects to the NIOS II. This breaks out a port which corresponds to the Avalon-MM bus from your QSys HDL module, which you can then directly drive with a state machine in your FPGA that serves as the Avalon-MM master in lieu of the Nios II. You will have to design your state machine to be a Avalon-MM master, refer to the document Avalon Interface Specification for relevant signals and timing diagrams.
With that being said, it may be excessive to implement an entire Avalon-MM interface for a UART. In this case, you should look into the many available open-source UART interfaces (assuming this is not for a class project where you have to implement it yourself). An example is a simple UART found on OpenCores.
The following links MAY be of use to you.
Zero guarantees.
UART / DE2 with links elsewhere
This looks useful Altera UART core overview. Chapter 8 in vaguely specified manual.
Do you have / are you using SOPC builder?
It SOUNDs to do what you want
The universal asynchronous receiver/transmitter core with Avalon® interface (UART core) implements a method to communicate serial character streams between an embedded system on an Altera® FPGA and an external device. The core implements the RS-232 protocol timing, and provides adjustable baud rate, parity, stop and data bits, and optional RTS/CTS flow control signals. The feature set is configurable, allowing designers to implement just the necessary functionality for a given system.
The core provides a simple register-mapped Avalon Memory-Mapped (Avalon-MM) slave interface that allows Avalon-MM master peripherals (such as a Nios® II processor) to communicate with the core simply by reading and writing control and data registers.
The UART core is SOPC Builder-ready and integrates easily into any
SOPC Builder-generated system. This chapter contains the following
sections:
■ “Functional Description” on page 8–2
■ “Device and Tools Support” on page 8–4
■ “Instantiating the Core in SOPC Builder” on page 8–4
■ “Hardware Simulation Considerations” on page 8–9
■ “Software Programming Model” on page 8–9
One level up above chapter plus many other modules
Using the DE2 JTAG UART about page 9 on.
