I'm designing a basic harness continuity checker based on shift registers implemented in Max V CPLDs. I'm aiming for a modular/extendable PCB design for the project as it has several benefits (cost, less complexity).
A uC communicates with my CPLDs using SPI. What I'm not sure about is how to best cascade these CPLDs in order to obtain a larger shift register. In a 144-pin TQFP, I only have 114 IO pins. Therefore, I can only implement a 114-bit Serial In Parallel Out or a Parallel In shift register. But by cascading these 114 IO devices I can obtain much larger shift registers.
However, I'd like to place these additional CPLDs on a different PCB. This has the advantage that I can simply extend the device when I need. On smaller harnesses, a single 114 test-point PCB will suffice. On larger ones, I can cascade. At the moment, the CPLD is really just a shift-register. But in the future I'm hoping to implement a state-machine that can possibly implement more functions, like checksum to verify the contents sent by the uC etc. But that's for later and all I know is that I'd just use SPI for communication.
As the CPLDs need SPI for communication, I am guessing that I need to pass these onto the cascading shift register i.e. each device will have a Serial Out (SO) pin. But it will also need to pass CLK, Chip Select and even a SI/MISO pin incase the uC needs to read back the shift register contents. Each CPLD will drive the next one in the chain by passing CLK, SO, CS.
I think buffering all the signals leaving the PCB would be necessary. But what would be the best way to actually connect the PCBs together? I suppose these really depends on the speed of operation. Fortunately, speed isn't an issue and therefore I'm operating at a very low frequency - just 62.5kHz. I'd like to be able to increase this, perhaps to 500kHz. I don't think I'll need any beyond that. At such frequencies, what's the best way to cascade PCBs?
Please note, I'm aware that I can purchase a large 324-pin device. I'm afraid, I can't really use that as there is no way to inspect BGAs here locally. So I'm sticking with TQFP packages.
I'm also aware that the topic, perhaps, mostly pertains to pcb-layout but I'm also hoping I can get some CPLD/FPGA centric advice here regarding what signals I need to send as I'm not so sure about that.
Would appreciate any responses.
Some more information based on Keven's answer:
The reason we feel daughter cards would benefit is most of the harnesses we assemble are have less than 70 wires. There are only 5 harnesses that have more than 250 wires. A single large circuit would be too costly. The reason the PCB would be large is because the mating connectors we use (62 pin D-Sub) are quite large physically.
So we thought of divinding the PCB by having a motherboard which houses the uC, LCD interface, CPLDs, SD Card, LED Controller etc. This would have about 62 or so test points.
The daughter card would also have 62 test points and it would only contain additional CPLDs and the connectors. This PCB would also be much smaller than the motherboard. The motherboard would be able to test 70% of our harnesses, with additional units allowing us to expand the test points when needed. Not only would this be cost-effective, it would also make the overall system much simpler. Chips, by themselves, are really cheap. The Max V 240Z that I'm using costs just $5. However, the cost for four-layer PCB is the limiting factor for us.
Each daughter-card would have connectors for programming the CPLDs and for connecting to the other PCBs. I don't feel programming each CPLD is much effort, especially because I won't really need to change any of the code. The uC won't even know the shift registers are cascaded... well, except, for the fact that I'd it to be able to sense the presence of additional PCBs so it knows the overall width. I think that shouldn't be too hard to do.