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I have doubt, What should be proper SDC constraint for CDC module, i.e., two flop synchronizer. between "dat driving by aclk to bdat1 driving by bclk" Note: aclk and bclk are not the same, also question for what if same too?

Is it false path?

enter image description here

Following is SDC constraints file I have used,

# Input ports
# -----------------------------------------------------------------------------
set_input_delay $ACLK_IN_DELAY  -clock $SCLK [get_ports dat ]  

set_input_delay $V_CLK_1_IN_DELAY     -clock $V_CLK_1    [get_ports srst_ni]  
set_input_delay $V_CLK_1_IN_DELAY     -clock $V_CLK_1    [get_ports drst_ni]  

# Output ports
# -----------------------------------------------------------------------------
set_output_delay $BCLK_OUT_DELAY  -clock $DCLK [get_ports bdat2] 
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  • \$\begingroup\$ What is your guess, and why? (We don't give plain answers to questions that smell like homework and ndon't show effort.) \$\endgroup\$ – Wouter van Ooijen Mar 18 '16 at 7:16
  • \$\begingroup\$ @Wouter : It is not home work, I am working with spyglass tool for cleaning cdc rule set, I have this module and as you can see, this module is used to prevent metastability. I am observing the error data loss on same or fast to slow clock domain crossing so what i guess is, it may false path so that it will not perform any timing checks on this path. If any standard constraints for this type of crossing is there then i want to know, nothing else. \$\endgroup\$ – Prakash Darji Mar 18 '16 at 8:04
  • \$\begingroup\$ If you haven't setup any timing constraints, there can't be any timing ignores or false paths. Can your tool generate a clock interaction report? \$\endgroup\$ – Paebbels Mar 18 '16 at 9:30
  • \$\begingroup\$ @Martin Zabel : Yeah sure! \$\endgroup\$ – Prakash Darji Mar 18 '16 at 11:04
  • \$\begingroup\$ What are the ports srst_ni and drst_ni? There seem to be not related to the design in the picture? \$\endgroup\$ – Martin Zabel Mar 18 '16 at 12:05
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Since its source clock is aclk and target clock is bclk, adat should be the only false path here. Other paths are valid and don't require any special constraint.

The false path can be defined to the data input pin of the second register (the one between adat and bdat1). I don't know how your tool treats the register names, but I used Synopsys' naming convention in the following example.

set_false_path -to bdat1_reg/D

There is a second way to define this false path. If the clocks are defined asynchronous to each other, adat will be false path automatically. I assume ACLK and BCLK are previously defined clocks.

set_clock_groups -asynchronous -group ACLK -group BCLK
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A two flip-flop synchronizes can be constrained with the follwing XDC lines. XDC is a Xilinx flavor for the commonly known Synopsis Design Constraint files (SDC).

set_property ASYNC_REG true [get_cells -regexp {gen\[\d+\]\.Sync/FF2}]
set_property ASYNC_REG true [get_cells -regexp {gen\[\d+\]\.Sync/FF1_METASTABILITY_FFS}]
set_false_path -from [all_clocks] -to [get_pins -regexp {gen\[\d+\]\.Sync/FF1_METASTABILITY_FFS/D}]

Source: sync_Bits_Xilinx.xdc

FF1_METASTABILITY_FFS is the first flip-flop (the meta stable one) and FF2 is the second flip-flop.


A generic 2-FF synchronizer implementation can be found in our PoC-Library as PoC.misc.sync.Bits, as well as two vendor optimized implementations for Xilinx and Altera. The above XDC code is relatively applied to all instances of PoC.misc.sync.Bits by setting the file property SCOPED_TO_REF to sync_Bits_Xilinx.

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  • \$\begingroup\$ I think the constraints given by you is for XDC not for SDC, so if I do cdc analysis for two flop synchronizer within non-xillinx platform like atrenta's spyglass, how should I constraint it? \$\endgroup\$ – Prakash Darji Mar 18 '16 at 10:51

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