Two-stage op-amp offset voltage constraint

Question

I have a question regarding the systematic offset voltage constraint for designing a two-stage op-amp.

Why must I_D6 equal I_D7 for offset voltage constraint?

The circuit and its offset voltage constraint are below:

Answer 1

1. This is only true of dc bias currents, not ac currents or transients.

2. We're assuming a "very high" load impedance, so the current flowing into the load is effectively 0.

3. We should really say that \$I_{d7} = -I_{d6}\$ because we want to use the passive current convention, which takes a pin current to be positive when it flows into the pin.

With these assumptions, \$I_{d7} = -I_{d6}\$ is just KCL written at the V_out node.

Answer 2

If we consider Q6 and Q7 to be a current source and sink respectively, they might be modelled like this:

^{simulate this circuit – Schematic created using CircuitLab}

On the left it's clear that this is an impossible situation. \$V_{OUT}\$ will be undefined, since two current sources in series will violate KCL if either source is even the tiniest bit different from the other. To model the roles of Q6 and Q7 more realistically, it's necessary to endow those sources with some finite impedance, which I do with R1 and R2, on the right.

It would also be appropriate to apply constraints to \$V_{OUT}\$, such that it can never exceed the positive supply (+12V), nor fall below 0V, which is the role of diodes D1 and D2. Their effect here will be to constrain \$V_{OUT}\$, which is the clipping behaviour described in the text.

Since Q7 is a current sink, small fluctuations at its gate will modulate drain current. I'll model this by replacing constant current sink \$I_7\$ with a varying current. It's a sinusoidal source, centered on 20μA, with amplitude 2μA:

^{simulate this circuit}

With two current sources in competition like this, each trying to maintain its own prescribed current in its own path, even the smallest of fluctuations in either will cause wild voltage swings at OUT. In other words transimpedance is very high. Here's what happens to \$V_{OUT}\$ (orange) as a result of \$I_7\$ (blue) fluctuating by only ±2μA:

Clearly, currents \$I_6\$ and \$I_7\$ have to be very similar in order for \$V_{OUT}\$ to reside between the extremes of 0V and the supply +12V, and for there to be sufficient room above and below to avoid clipping. This is why the author states the requirement \$I_{D7} = I_{D6}\$.