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I have a question regarding the systematic offset voltage constraint for designing two-stage opamp.

My question is : Why must Id6 equal Id7 for offset voltage constraint ?

Please find below the circuit and its offset voltage constraint:

Two-Stage opamp

Offset Voltage constraint

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  1. This is only true of dc bias currents, not ac currents or transients.

  2. We're assuming a "very high" load impedance, so the current flowing into the load is effectively 0.

  3. We should really say that \$I_{d7} = -I_{d6}\$ because we want to use the passive current convention, which takes a pin current to be positive when it flows into the pin.

With these assumptions, \$I_{d7} = -I_{d6}\$ is just KCL written at the Vout node.

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