# Two-stage opamp offset voltage constraint

I have a question regarding the systematic offset voltage constraint for designing two-stage opamp.

My question is : Why must Id6 equal Id7 for offset voltage constraint ?

Please find below the circuit and its offset voltage constraint:

3. We should really say that $I_{d7} = -I_{d6}$ because we want to use the passive current convention, which takes a pin current to be positive when it flows into the pin.
With these assumptions, $I_{d7} = -I_{d6}$ is just KCL written at the Vout node.