# what happens when the carry bit is zero in addition/subtraction algo for hardware This is the algorithm in flow diagram for addition and subtraction in computers.

A(s) is the sign bit of A
B(s) is the sign bit of B

//(s) denotes the subscript

E is the register that has a carry bit AVF is the register that carries the overflow bit. A + As is the accumulator register. (A saver !) Initially the XOR operation is carried that checks if the sign bit of two numbers is same or not.

I understand this algorithm except the circled part. What is happening when E = 0 ? Please explain taking a simple example.

• there should be an algorithm tag in electronics.stackexchange.com – Suhail Gupta Nov 17 '11 at 14:06
• That diagram looks more complicated than it ought to be. For subtraction you need just to complement B and consider the Borrow flag of subtraction be the complement of the Carry flag. Then you can just use addition. – starblue Nov 17 '11 at 19:35
• @starblue: I agree; this looks unnecessarily complicated. – davidcary Nov 18 '11 at 3:25
• @ davidcary @ starblue then can you please give a more modern flow chart – Suhail Gupta Nov 18 '11 at 7:38

What is happening is:

1. A is inverted.
2. A has 1 added to it.
3. A is inverted again.

This generates what is called the "Two's Complement" of the number in A.

Two's Complement is a way of encoding negative numbers in binary.

• @ Majenko what is the need to encode here ? What do i get after encoding ? – Suhail Gupta Nov 17 '11 at 16:14
• Description "3." above is wrong. A is not inverted again, as the last line in the flow chart is inverting A(s) which is described as the sign bit for A, not inverting A proper. Steps 1. and 2. alone do do a 2's complement, thus negating the numeric value in A. A(s) seems to be a separate register. – mgkrebbs Nov 18 '11 at 7:46
• I find it very hard to see the esses on the diagram, the size and quality is too low. – Majenko Nov 18 '11 at 7:59

The vast majority of modern ALUs are "two's complement" adders, which don't need the "extra" steps you circled.

This looks like a sign-and-magnitude ALU, which I haven't seen in years.

Let's say we are subtracting (+7)-(+9). In sign-and-magnitude format, we have

As = +; A = 0000_0111 (represents +7 in sign-and-magnitude notation)
Bs = +; B = 0000_1001 (represents +9 in sign-and-magnitude notation)


The first decision compares the signs. Since +7 and +9 have the same sign (both positive), we go down the operations on the left:

EA <- A + !B + 1 = 0000_0111 + 1111_0110 + 1 = 0_1111_1110


so now

E = 0; A = 1111_1110


This is the two's complement representation of the result. A two's complement ALU pretty much finishes here. This flowchart illustrates a sign-and-magnitude ALU, which takes a few more steps:

Since that carry bit E is now 0, that implies that A was originally less than B, so we need to do a special fix-up to convert from two's complement notation to sign-and-magnitude notation:

A <- !A + 1 = !(1111_1110) + 1 = 0000_0001 + 1 = 0000_0010
As <- !As = !(+)


so we end up with

As = -; A = 0000_0010 (represents -2 in sign-and-magnitude notation)


Is that the correct result for (+7)-(+9) ?

oh i explain! actually u have to do a simple subtraction first what is the value of 4-12 i.e -8 now come in binary equivalent of above decimal subtraction 4= 00100 12= 11000 -12= 2s comp of 11000 i.e 00111+1=01000 now 4-12= 4+(-12)= 00100+01000= 01100 and 01100= 12 :O but 4-12!=12!!!!!!! actually if 0 is in 1st bit i.e in carry bit e=0 we have to make the 2s comp of ans to got the actual answer so 2`s compliment of 01100= 10011+1= 10100 1st bit 1 denote that the answer commes was negative and rest denote the answer i.e inn 10100 10100 means -ve 0100 i.e. -8 which is our real answer :) hope you got