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When referring to DDR/DDR2/DDR3/DDR4 memories, I am not able to understand the difference between memory clock and I/O clock.

As per: https://en.wikipedia.org/wiki/Double_data_rate

DDR-200 - Memory Clock = 100 MHz, I/O Bus Clock = 100 MHz;
DDR2-800 - Memory Clock = 200 MHz, I/O Bus Clock = 400 MHz;
DDR3-1600 - Memory Clock = 200 MHz, I/O Bus Clock = 800 MHz;
DDR4-3200 - Memory Clock = 400 MHz, I/O Bus Clock = 1600 MHz

Could someone please explain what is memory clock and I/O bus clock here? Because I understand that memory controller provides only a single clock to the memory chip, which is half that of the data rate.

Thank you.

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3 Answers 3

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I/O bus clock is always half of bus data rate.
example: DDR2-800: bus data rate is 800 MT/s, IO clock is 400 MHz.

Memory clock is the clock which sync memory controller:
DDR1: 1/2 of bus data rate, because of 2n-prefetch
DDR2: 1/4 of bus data rate, because of 4n-prefetch
DDR3: 1/8 of bus data rate, because of 8n-prefetch

Two different clock in DDR for MC (memory controller and PHY):
DFI clock: value is equal to memory clock
DFI PHY clock: value is equal to IO clock

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  • \$\begingroup\$ Thank you, that was helpful. So to summarize, for example in case of DDR2-800, bus data rate is 800 MT/s (which is mentioned in its name), IO clock is half that at 400MHz, and the memory clock is 1/4th at 200MHz. (Memory clock ---> I/O Bus clock ---> Bus data rate). Mentioning all this just for myself. \$\endgroup\$
    – LoveEnigma
    Commented Apr 22, 2019 at 10:44
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DDR,DDR2 and DDR3 memories follow the DDRxxx/PCyyyy classification.

The real clock of DDR, DDR2, and DDR3 memories is half of the labelled clock speed. Therefore DDR400 memories work at 200 MHz, DDR2-800 memories at 400 MHZ.

The bus clock rate is the actual speed of ur FSB(The FSB connects the processor (CPU) in your computer to the system memory).

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  • \$\begingroup\$ Thanks, Prakash. But that still does not answer my original question, as to what is memory clock and what is I/O clock when referring to DDRx memory? I actually understand memory clock, which is provided by the memory controller and is half the data rate, but as per Wikipedia the memory clock for DDR2-800 is 200MHz and I/O clock is 400MHz. Why is that? What is the I/O clock then? Why is the memory clock 1/4th of 800? \$\endgroup\$
    – LoveEnigma
    Commented Mar 25, 2016 at 6:31
  • \$\begingroup\$ I think it should be the frequency at which IOs (pins) are droved by memory controller, so it is at DDR frequency of operation at which read or write data. \$\endgroup\$
    – Prakash Darji
    Commented Mar 25, 2016 at 6:57
  • \$\begingroup\$ Memory clock, provided by system to memory, as It is DDR2-800, its Data rate (MT/s) is 800 MT/s, for that DDR I/Os frequency should be 400MHz, as it is DDR to produce R/W at 400 MHz it is fed with 200 MHz. \$\endgroup\$
    – Prakash Darji
    Commented Mar 25, 2016 at 7:02
  • \$\begingroup\$ Thanks for the answers. I think I understood it just OK. \$\endgroup\$
    – LoveEnigma
    Commented Mar 29, 2016 at 4:32
  • \$\begingroup\$ Memory clock is the actual clock provided by the memory controller to the memory chip, which is 200MHz for DDR2-800 chip. The IOs operate at a frequency of 400MHz, and since it is DDR, the actual data transfer rate is 2 x 400 = 800MT/s. But since you have asked, I have one question. When we refer to data being clocked twice per cycle, people are always talking about the IO clock and not the memory clock provided by the memory controller, right? \$\endgroup\$
    – LoveEnigma
    Commented Mar 29, 2016 at 4:37
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The memory clock is the clock at which the DRAM core operates. The prefetch feature allows the memory core to operate at 1/2-1/8 of the bus data rate.

For example, for the 8n case, the DRAM core will retrieve 8 x n (IO width) in one DRAM clock cycle. This technique costs DRAM a wider global IO (GIO) but the DRAM can run at 1/8 speed. The IO clock at 1/2 data rate will serialize the parallel GIO into the full data rate.

This is mostly transparent to the memory interface and helps the DRAM core run slower.

DDR1: 1/2 of bus data rate, because of 2n-prefetch DDR2: 1/4 of bus data rate, because of 4n-prefetch DDR3: 1/8 of bus data rate, because of 8n-prefetch

I am not 100% sure whether the memory controller at the host side has to run at the same speed as the DRAM core. Any other folks can help us?

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