For Vin below threshold voltage, M1 isn't conducting, neither does M2 since Id=0. So what happens circuit wise, how come that Vdd=Vout ( we did this in class)?
Note that M1 is N channel while M2 is P channel, although they both invert from gate to drain in this configuration.
With Vin at 0, M1 is off. With the gate of M2 at 0, M2 is presumably on. I say "presumably" since you have provided no specs on Vdd and the required gate voltage for M2 to be on. I'm assuming these have been arranged such that a P channel FET with source tied to Vdd is on when its gate is at 0 V.
From above, replace M1 with a open switch and M2 with a closed switch. Vout is now obvious. Draw it out as open/closed switches if that helps you see it.