For my master thesis, I need to measure the propagation delay of the modules of my implementation. I use Quartus II to do so. My goal is to measure the critical path of my modules. I have read a lot of topics that say that I need to use the TimeQuest Timing Analysis tools but it is too complex for me (I'm more a computer science engineer than en electrical one). I search and I have found that Quartus performs a computation of the propagation delay which is what I need. I have found on this website all the details :


Unfortunately, it doesn't answer all my questions. Effectively, I can clearly see what is a transition from rising edge to falling edge (a transition from 1 to 0) and from falling edge to rising edge (a transition from 0 to 1). However, I cannot see what is a transition from rising edge to rising edge and from falling edge to falling edge. I suppose that it doesn't mean that the signal doesn't change (since there wouldn't be any propagation delay).

Can someone explain me what is this transition ?

Thank you !

  • 1
    \$\begingroup\$ "a transition from rising edge to falling edge" is not "a transition from 1 to 0" because a transition from 1 to 0 only involves one edge i.e. it is the fall time. \$\endgroup\$
    – Andy aka
    Commented Mar 23, 2016 at 11:20
  • \$\begingroup\$ Ok, I see what you mean. Is that correct that a transition from a rising edge to a falling is a transition from 0 to 1 then from 1 to 0 ? \$\endgroup\$ Commented Mar 23, 2016 at 11:28
  • \$\begingroup\$ @user1382272 Easy: The transition from 0 to 1 is a rising edge. \$\endgroup\$
    – Dzarda
    Commented Mar 23, 2016 at 11:35
  • \$\begingroup\$ If you don't have concern about rising and falling edge and you only have concern about timing analysis (propagation delay) only then Quartus II will generate one report in Time-quest which will specify critical to short all path timings, but keep in mind that it is specific to platform (board) you are supposed to give at New Project Wizard. \$\endgroup\$ Commented Mar 23, 2016 at 12:25
  • \$\begingroup\$ @PrakashDarji This is exactly what I need. I have specify a platform and I will perform all my measurement on it. Do you remember in which directory I can fin the critical path timings ? \$\endgroup\$ Commented Mar 23, 2016 at 14:22

1 Answer 1


I think you have transition times and propagation delays mixed up.

Transsition time refers to the speed of edges, while propagation delay refers to the time it takes for a signal to go through some device.

For example, output transition time generally refers to the time it takes for an output edge to go from a high to a low or from a low to a high (two different spec's by the way), while input transition time refers to the maximum time allowable for an input to be driven from a low to a high or from a high to a low and still have the device meet its switching time specs.

Propagation delay is an entirely different thing and and is the time it take for a device's output to go high (or low) once its input has been driven.

For example, consider an ideal inverter with a maximum propagation delay of 10 nanoseconds with an input which has just transitioned through Vcc/2. In order to meet the 10 nanosecond propagation delay spec, its output must transition through Vcc/2 in less than or equal to 10 nanoseconds.

But, since a picture is worth a thousand words, from TI,

here's the crux of it

enter image description here

  • \$\begingroup\$ Thank you for your additionnal information. I have learned what it is the propagation delay but not the transition time ! \$\endgroup\$ Commented Mar 23, 2016 at 14:23
  • \$\begingroup\$ Right, but that data sheet was published in 1982 when vendors actually supplied printed books. Today, you get a URL that is no longer accessible. Also, the FPGA tools seem to mix up the two terms. In an SDC file they use the terms 'rise' and 'fall' for clock input delays. These are a little nebulous or rather they count both. For Quartus and slew, you need 'INPUT_TRANSITION_TIME' to note rates slower than the TTL input capabilities. \$\endgroup\$ Commented Nov 21, 2023 at 21:50

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