Is using vias for split data buses a bad idea?

Question

I've tried searching for this but can't seem to find the answer I'm looking for. I'm designing my first PCB and I'm having trouble routing data lines without making the board large.

For example, I have two ICs that need to have 8-12 data lines between them. 7 of the lines line up perfectly and I can rotate the two ICs to support that. But the other lines are becoming difficult to route without enlarging the board.

I can post pictures if needed by my question is more generic.

Based on tutorials I've found, I try to keep my ground traces on the bottom layer and data traces on the top (only a two-layer board, all through-hole).

So I was wondering, if I have a trace that needs to run over another trace on the same layer, is it advisable to put a via in just before it, run it "under" the trace, and then another via back up? Basically a data trace on the top would temporarily go to the bottom layer, cross under the top trace and then back up.

I hope that makes sense.

It is my understanding that this is exactly what vias are for. But I didn't want to use them all over the place if it's bad practice.

Keep in mind that I've rotated the ICs every which way I can.

Oh, for what it's worth, this is an audio board and the two ICs are a 74x595 shift register and a AY-3-8912 audio IC with a max clock speed of 2-4MHz.

Thanks for any suggestions.

Answer 1

It will probably be fine in your case to via down to the bottom layer and have a small slot in the ground plane. If you were running higher speed signals it could become a problem.

The issue to generally be concerned about with cutting a slot in the ground plane is that return currents will need to go around the slot, which can then act as an antenna and be an EMC problem. Return currents are concentrated on the paths of lowest impedance. For low frequencies, this is the path of lowest resistance. For high frequencies, inductance starts to dominate the impedance, so the return currents will flow in the direction that minimizes the loop area. This means that they will be concentrated directly underneath the signal trace until they reach the slot, then flow around to get back to the signal trace again. This will cause radiated energy and distort nearby signals (or farther nodes if they are high-impedance). With lower frequencies, the return currents will not even care to get close to the slot, though, instead making a diamond shape of lower current density centered on the slot.

That being said, 2-4 MHz is so slow I wouldn't worry about it. If you're running at 500+ MHz with fast edge rates, though, slots in the ground plane should be avoided, especially underneath high speed data lines.