# CMOS tri-state buffer internal structure

I was trying to understand the CMOS tri-state buffer internal structure with logic gates...

The image is similar to this one:

Anyway, I'm not understanding the logic I think something is escaping:

• So imagine that I put the Enable in Low (0). In the NAND it will appear a Low and whatever the value I choose for the Input I will get a Low that will be negated and become a High (1)... But won't that activate the circuit? And when the control is 0 it shouldn't right...

The NOR function appears to work correctly...

Sorry if this is a kind of dumb question I'm starting my studies about digital systems...

Thanks!

• Looks like a lot of Boole to me. – Tim Spriggs Mar 25 '16 at 14:44
• The top transistor is a PMOS and is therefore OFF when 'high' is applied. – pjc50 Mar 25 '16 at 14:46
• Thanks! I understood now. Just another question: is the value that "activates" the transistor related to the value of the Output? Because if I choose the input "high" and the control "high" I will activate the top transistor in "low" but the output value should b e "high". So it's not related, right? – Granger Obliviate Mar 25 '16 at 15:18
• No the control voltage of a MOSFET is between gate and source. In this case the PMOS source terminal is the one tied to the positive supply voltage. – The Photon Mar 25 '16 at 15:37

Since I just explained this to my daughters.

The bottom transistor is an NMOS transistor (an N-channel CMOS transistor). It works as a voltage-controlled switch. If the gate (the middle pin) is high (> 1V or so), it acts as if you pressed a push-button. It is ON. Otherwise, it is OFF.

The upper transistor is a PMOS transistor. It works in the opposite way. It is OFF when the gate is HIGH, and ON otherwise.

For the lower logic, the output is connected to ground when the NMOS is ON. It is ON when NOR(d, NOT(e)) = !(d + !e) = !d !!e = !d e = AND(NOT(d), e). I.e., the output is LOW (connected to ground) when the data is LOW and enable is HIGH.

For the upper logic, the output is connected to VDD (HIGH) when the PMOS is ON. It's ON when the gate is LOW. The input is NAND(d, e) = !(de). So, it is ON when both data is HIGH and enable is HIGH.

So, as far as I can see:

| enable | data | output |
|   L    |   L  |   Z    |
|   L    |   H  |   Z    |
|   H    |   L  |   L    |
|   H    |   H  |   H    |


Notice the Z output. When the enable-pin is low, the output pin is not connected to anything, i.e. it is floating.

An N-channel MOSFET, such as the lower one in the picture, will conduct when the voltage on the gate is at least 0.7 volts higher than voltage on either the source or the drain. A P-channel MOSFET, such as the upper one in the picture (notice the circle on the gate) will conduct when the voltage on the gate is at least 0.7 volts lower than either of the other two voltages. N-channel MOSFETs are used for low-side drive because with the source at ground they can turn on by putting the gate high. P-channel MOSFETs are used for high-side drive because with the source at VDD they can turn on by putting the gate low.

It is possible to construct devices with N-channel MOSFETs on the high side (indeed, many famous processors like the Z80 and 6502 were implemented that way) but high-side drivers tend to be rather feeble. If a chip used an NMOS transistor as a high-side driver and its gate was at VDD, it would start to turn off as the output approached VDD-0.7 volts. Further, if the chip doesn't have any source of voltage higher than VDD available to it, it will have some difficulty getting the gate of the output FET all the way up to VDD. One of the innovations in the 6502 was that the process used to make it could cause transistors to be a little bit "leaky", so an inverter which used a leaky pull-up transistor and a switched pull-down resistor could get reasonably close to VDD, but there is still a huge difference in drive strength between the high-side and low-side output transistors. By contrast, many CMOS devices have transistors that are much closer to being balanced.