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I'm writing a VHDL code for an integer to float converter using variables. I have simulated it and the results match expectations. However, when looking to compile and synthesize using Precision RTL from Mentor Graphics, I'm encountering the following error:

The slice width in the variable part select expression is non-static. If this a genuine case then use simpler expressions instead.

This error refers to the below line of code:

sig_float_out(WIDTH*2-5 downto 0) <= int_input(first_one_at downto 0) & int_input(WIDTH-1 downto first_one_at+1);

It seems to me that my expression is locally static and should have no problem synthesizing since I am only looking to swap content around a predetermined variable.

If this is not the case some clarifications and modification options would be appreciated.

The complete code for reference:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity lab4 is
    port(
        int_input    : in  std_logic_vector(3 downto 0);
        float_output : out std_logic_vector(7 downto 0);
        underflow    : out std_logic
    );
end lab4;

architecture int_to_float of lab4 is
    constant WIDTH   : integer := 4;
    signal sig_float_out : std_logic_vector(WIDTH*2 - 1 downto 0);
    signal check  : integer;
begin
    process(int_input)
        variable first_one_at  : integer;
        variable bool_flag   : boolean;
        variable input_2comp : std_logic_vector(WIDTH - 1 downto 0);

begin
    first_one_at := 0;
    bool_flag  := false;
    underflow <= '1';

    if (int_input = "0000") then
        sig_float_out <= (others => '0');
        underflow    <= '0';
    elsif (int_input(WIDTH - 1) = '0') then
        for i in WIDTH - 1 downto 0 loop
            if (int_input(i) = '1') then
                if (bool_flag = false) then
                     first_one_at := i;
                      bool_flag := true;
                end if;
            end if;
        end loop;

        sig_float_out(WIDTH*2-1) <= int_input(WIDTH -1);
        sig_float_out(WIDTH*2-2 downto WIDTH*2-4) <= std_logic_vector(to_unsigned(first_one_at + 1 + 3, 3));
        sig_float_out(WIDTH*2-5 downto 0) <= int_input(first_one_at downto 0) & int_input(WIDTH-1 downto first_one_at+1);

    else
        input_2comp := std_logic_vector(unsigned(not(int_input))+1);
        for i in WIDTH - 1 downto 0 loop
            if (input_2comp(i) = '1') then
                if (bool_flag = false) then
                            first_one_at := i;
                            bool_flag := true;
                end if;
            end if;
        end loop;
        sig_float_out(WIDTH*2-1) <= int_input(WIDTH -1);
        sig_float_out(WIDTH*2-2 downto WIDTH*2-4) <= std_logic_vector(to_unsigned(first_one_at + 1 + 3, 3));
        sig_float_out(WIDTH*2-5 downto 0) <= input_2comp(first_one_at downto 0) & input_2comp(WIDTH-1 downto first_one_at+1);
    end if;

        check<=first_one_at;
end process;
float_output <= sig_float_out;

end int_to_float;   
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  • 1
    \$\begingroup\$ The problem is that "first_one_at" is a variable, so your slice widths and thus the wiring of the resulting hardware is unknown at synthesis time. What you're doing looks like a rotate operation, perhaps see if your synth tool accepts rotate operators (ROL,ROR?) \$\endgroup\$ – Brian Drummond Mar 25 '16 at 15:09
  • \$\begingroup\$ The non static feature that you are mentioning (variable down to 0) is supported in verilog for the Precision RTL. For vhdl, Precision RTL supports cases where the difference of the left and right indices is an integer. \$\endgroup\$ – user115331 Jun 29 '16 at 9:58
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You can't do variable slicings in synthesis, because the expression has no preknown range and size. Even if allowed in subexpressions, it's hard to ensure that all subexpressions together meet the LHS constraints for every possible input.

And a further question would be: What's the resulting hardware for that construct? A very big ROM?

You need to convert your code to

  • a multiplexer or
  • mask + shift operations
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