I am trying to design a low power, fully Differential Input Single Ended Output amplifier with gain of atleast 50dB. I am using a VDD of 1.5 Volts using MOSFETS. I want to have maximum swing and my circuit along with different node voltages and MOSFET Parameters are shown in the attached picture. I want to have Vdsat for each and every MOSFET to be around 0.1~0.12 Volts. In the picture, the very first Voltage source that is connected to 2nd matched PMOS pair is vbias3 variable. The second Voltage source which is currently set to 1 V is vbias2 variable and the tail source biasing voltage source is vbias 3 variable. Later I will replace all of these voltage sources with a biasing generator that I will design later. The two matched pair NMOS (T-6,0,5,8) have channel width of 4uM and PMOS (T-1,4,2,3) transistors have Channel width of 8uM. The Tail current source NMOS T7 has channel width of 8uM. All of the transistors have channel length of 220 uM.
I am trying to have my output (the middle node between T1 and T0) to be at centre of the rail voltage (1.5V) so that I can maximize my swing. However I am stuck at this point and no matter what I do I can't bring that point down to ~750mV and have the gain of 50dB.
Need design help with following: - Bring down the Vdsat for top 4 PMOS to around 0.1~0.12 V - Bring the output node(currently at 1.037 V) down to 750 mV by keeping the gain as high as possible to maximize the swing. - Have all the MOSFETS operate in saturation
NOTE: Please don't worry the Tail current source NMOS as Vdsat seems to be greater than VDS in the current screenshot, however I can easily put my MOSFET in saturation by just bringing the biasing voltage down by 5mV.
Any help to achieve the above requirement would be greatly appreciated.
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