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I'm getting some pretty noisy data from a 12-bit I²C ADC (MAX11617 to be precise). Though it's most likely some very sub-optimal board layout that's introducing a lot of noise to the analog signal, I'd like to rule out a one particular thing first.
When I write software for a µC there's usually some bit in some ADC control register that indicates, that the ADC is done sampling, so it's safe to go on and read the data. In this particular case, it's a TI sitara processor running Linux so the readout is done over the I²C bus by just grabbing the data off of /dev/i2c-* like so:

read(m_fd,tmpBuf,24)

Since I have very limited control over the I²C bus in this case, is it possible that I'm requesting data while the ADC is still sampling? The datasheet only says

Once all conversions are complete, the MAX11617 release SCL, allowing it to be pulled high. The master can now clock the results out of the memory in the same order the scan conversion has been done at a clock rate of up to 1.7MHz.

Can I safely assume that the Linux I²C driver is taking care of this?

(I wasn't sure whether electronics.stackexchange.com or stackoverflow.com was the proper place for this question so please excuse me if I'm off-topic here.)

Any input or pointer are greatly appreciated!

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    \$\begingroup\$ If you short the ADC input to ground does it read 0, or 0 + noise? \$\endgroup\$
    – user16324
    Mar 26, 2016 at 20:41
  • \$\begingroup\$ I cannot tell you that atm since the hardware is far, far away. But that's a great idea, I'll test that as soon as I can! \$\endgroup\$ Mar 26, 2016 at 20:57

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Can I safely assume that the Linux I²C driver is taking care of this?

Yes, the TI Sitara kernel has full support for the so called I²C "clock stretching" that some chips use.

They don't allow infinite clock stretching and will report a bus error if the clock line stays low for longer than a defined period, but we're talking about seconds here, so no issue for your ADC.

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