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I have always used VHDL and now need to use Verilog, so I'm learning Verilog.

How can I create and use user-defined data type in Verilog for state machines?

For example, in VHDL I would write something like:

VHDL example:

       type Command_Byte_state_type is (C0,C1,C2,C3,C4,C5);
       signal Command_Byte_state : Command_Byte_state_type;

Verilog equivalent:

       parameter State0=0, State1=1, State2=2, State3=3, State4=4 ;

My question is , do you have to assign a 0 /1/2/3/4 value to the defined parameter ?

How can I define my own data type in Verilog and use it like in VHDL?

Naming convention becomes so much easier when doing this in VHDL. Also, I can easily change the state machine implementation to one-hot, gray or any other, by just selecting an option in synthesis.

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  • \$\begingroup\$ I don't think Verilog does what you want. Parameters in your example define shorthand names for certain constant values, but they don't change anything about the registers you might use to hold those values. \$\endgroup\$
    – The Photon
    Mar 26, 2016 at 23:18
  • \$\begingroup\$ But then, there's no such thing in real hardware as a set of 3 flip flops that are only capable of holding 5 values. \$\endgroup\$
    – The Photon
    Mar 26, 2016 at 23:21
  • \$\begingroup\$ I like verilog, and as I only edit or use VHDL, Im probably not the best to comment, but I think you are seeing the pros and cons of the languages. Personally, I love Verilog, but VHDL may be a safer language? \$\endgroup\$
    – johnnymopo
    Mar 27, 2016 at 17:03

1 Answer 1

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SystemVerilog has enumerated types, and most synthesis tools now support this:

typedef enum {C0,C1,C2,C3,C4,C5} Command_Byte_state_type;

Command_Byte_state_type Command_Byte_state;

And you will be able to select the encoding options in your synthesis tool the same way you do when writing VHDL.

If you insist in staying with Verilog, you will have to assign a default encoding 0/1/2/3/4, but you can still tell the synthesis tool to remap it.

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