I have always used VHDL and now need to use Verilog, so I'm learning Verilog. . .
How can I define and use user-defined data type in Verilog for state machines.
for eg : In VHDL I would write something like below
VHDL example :
type Command_Byte_state_type is (C0,C1,C2,C3,C4,C5); signal Command_Byte_state : Command_Byte_state_type;
Verilog equivalent :
parameter State0=0, State1=1, State2=2, State3=3, State4=4 ;
My question is , do you have to assign a 0 /1/2/3/4 value to the defined parameter ?
How can i DEFINE OWN DATA type in Verilog and use it like in VHDL ? Naming convention becomes so much easier when doing this in VHDL. Also, I can easily change the state mc implementation to one hot / gray or any other, by just selecting an option in synthesis.