I've been given the task to design a multistage transistor amp.
Specs given are:
- Overall voltage gain: 80 (min) to 100 (max)
- Input resistance no less than 1Mohm
- Voltage supplies: +-10V
- Achieve max output voltage swing when Load Resistance is 2kohm
- Capacitive coupling with low freq cut off of no lower than 30Hz but no greater than 60Hz
- Amp must also include negative feedback from final stage to an earlier stage (preference: voltage-voltage/voltage-series)
[PS. I am aware I don't need the emitter cap in stage 2 of the design above; I believe I must split the emitter resistor into two separate resistors for the negative feedback I'm hoping to implement.]
I'm trying to design the first stage using JFET, but haven't been able to design it very well.
From the data sheet, I see the typical values for IDSS and VGSoff are 10mA and -8V (Although in the lab, actual VGSoff seemed to be = -4V).
Keeping this in mind, I calculated values of resistors:
Assuming RD = 4.5k and RL=10k, I calculated RS = 350ohm. This didnt seem to work in simulation in PSpice or when I built it in the lab.
Is there a way to calculate RD/RL instead of assuming values?
However, I have a question regarding biasing in my case. I went with R1=R2=2Meg (for low freq response). Still didn't work.
Which, from Self-Bias and Voltage divider at gate, seems like the best way to go in my design?
Even if I get values, I could calculate backwards and see how the theory works out.
Help much appreciated!