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We're building a BMS that has a micro on each cell in the pack. I know this isn't standard and the issues that come with it, however the pack isn't a standard layout, and the benefits out weigh the issues (if I can figure out solutions ;) )

The main issue I'm stuck on is connecting micros at different voltage levels to the same I2C bus (actually SMBus) at a reasonable cost (aiming 50c, any lower is a bonus)

Ideas looked at:

Opto/Capacitive isolation

Opto/capacitive isolation for each channel, while this is by far simplest I believe this is too expensive $2 per channel. (Happy to be corrected)

(very useful resource for those interested AN10364: Opto-electrical isolation of the I²C bus www.nxp.com/documents/application_note/AN10364.pdf)

Level Shifters

schematic

simulate this circuit – Schematic created using CircuitLab

The obvious first place to look is at gnd:3.3V -> gnd:5V level shifters that are used in i2c networks, there are two ways I can see these be used, but with their own issues.

Daisy Chain

schematic

simulate this circuit

If you level shift between each cell, you get low voltage shifts (making it lower cost) and infinitely scale able (in theory) in terms of cells in series.

However, you don't have common grounds, So while it works in one direction (3.3v signal pulls the 5v signal low) it doesn't in the other (5v can't pull the 3.3v signal low)

Branches

schematic

simulate this circuit

With this design, it effectively a direct replacement for the opto/cap isolation. It goes from what ever the voltage is at the cell down to 3.3V on the i2c bus. This should fit closer to the traditional level shifter, but when the signal drops to digital O on the high side, it should only drop to the cell voltage,

enter image description here

As opposed to all the way to ground. enter image description here

Intrigued to know if

a) I've totally missed an easier way of doing this,

b) If anyone has any helpful pointers to anyone who's done this before,

c) I'm a bubbling buffoon and it'll never work.

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  • \$\begingroup\$ I think you will be severely limited in the made-for-purpose I2C translator chips available when the bus voltage goes above 6 or 7 V, making the discrete transistor option the most viable one for your situation. I'm sure you can find a MOSFET for under $0.25 if you look around. If you didn't have the "high" voltage requirement, I'd look to using a I2C switch part. Most of them allow level translation and so you could fan out to 4 or 8 different busses with a single part priced below $1. \$\endgroup\$
    – The Photon
    Mar 28, 2016 at 4:25
  • \$\begingroup\$ Have you seen any translator chips that didn't require common grounds? I could keep it within 6-7V with the daisy chain approach potentially. Otherwise yeah, I was expecting to go discretes, didn't know if anyone had seen a closer circuit than the basic level translator to get me started. \$\endgroup\$ Mar 28, 2016 at 4:54
  • \$\begingroup\$ OK, now I look I understand what you mean about common ground. If you don't have a common ground, then neither the discrete transistor nor the IC solution will work. There might be an optocoupler based solution that could work, but you're going to have to throw your $0.50 target out the window if you aren't making a few million of these. \$\endgroup\$
    – The Photon
    Mar 28, 2016 at 4:59
  • \$\begingroup\$ See NXP's AN10364: Opto-electrical isolation of the I²C bus; this isn't cheap. If possible, consider using some bus with unidirectional signals (UART, SPI, etc.) instead. \$\endgroup\$
    – CL.
    Mar 28, 2016 at 7:30
  • \$\begingroup\$ Cheers CL, I'll add that to my question as it's a useful resource I looked at previously, but as you said, too expensive. And unfortunately needing bi-directional comms \$\endgroup\$ Mar 29, 2016 at 6:28

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If you use the MOSFET level shifter with the battery pack in either case you propose something will get fried.

The MOSFET level shifters only work if all the pieces are referenced to ground. When this shifter is connected between two different voltage devices, low state for each device is ground. In your case each cell above the lowest one does not have a ground reference.

For example cell 2 has a reference at 3.7v. When the main micro switches the bus from high state to low state (ground) the main micro would drag the line of cell 2 to ground which is -3.7v below it's reference. Something will fail. As the cell count goes up the problem gets worse.

Unfortunately your only options involve optos. If you want to keep SMbus then the NXP buffer solution with optos is best, as mentioned in the comments. If you want a simpler solution then switch to a unidirectional system like UART, as suggested in the comments. This would need less optos and by slowing down the speed, cheaper optos could be used.

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  • \$\begingroup\$ Yeah thanks Vini, I got that far, just looking for alternatives to Optos. Points for explaining it better than me though! \$\endgroup\$ Mar 29, 2016 at 6:40

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