# Assigning x in verilog

Assume there exists a 1 bit data output port and a 1 bit dataValid output port for a module. Is it OK to assign 1'dx to the data output when dataValid is assigned 0? Will this create synthesis issues?

EDIT: X optimizations seem to happen in both Synopsys DC and Cadence RC. Consider this code (a and b are 1-bit inputs and c is a 1-bit output).

always_comb
if ( !a && !b ) c= 0;
else if ( a && !b ) c = 1;
else if ( !a && b ) c = 1;


gives an OR gate which is an optimized solution as opposed to an XOR which would have been inferred if c were set as 1'd0. This is a simple example but it seems to prove that synthesis tools do perform X optimization. Considering nasty X propagation bugs and verification troubles, are X assignments worth the saved area?

• OR is probably no more or less efficient than XOR. I think the only reason it chooses XOR is because the if-elseif-elseif tree is converted to a series of multiplexers with the last else ignored which leads to the value in the penultimate elseif statement. If you made the penultimate line else if ( !a && b ) c = 0;, it would probably result in c being 0 when a and b are 1 – Tom Carpenter Mar 29 '16 at 13:03

Never assign an X in a reachable code-path, only use X for propagating simulation unknowns. This will make life slightly easier in the long run. If you want to optimise don't care logic, do that explicitly (and pick the optimum value for the unused state). That way, you get consistent behaviour more of the time (hopefully always)

• In some cases it's very difficult to identify the easiest implementation and doing it can make the code very confusing. Also, why go through the trouble if the tool can do it for you? – pc3e Mar 16 '18 at 16:17
• If you know what you're doing, it may be OK. Otherwise, defensive code may be safer and more reliable. Unless you have exhaustive proof of correctness. – Sean Houlihane Mar 16 '18 at 16:19
• I prefer reliable code over micro-optimisation. – Sean Houlihane Mar 16 '18 at 16:22
• While I agree with that philosophy I'm not convinced that it applies here. I assume the problem you see is that using don't cares could give you a circuit that produces '0 for a given set of inputs in one compilation, then '1 in the next. If you hit this condition in simulation and get 'x propagation, you will see the problem immediately. If you are not hitting the condition, what makes you sure that whatever behavior you have coded ('0, '1, the old register value, etc.) provides the correct behavior? – pc3e Mar 16 '18 at 16:51
• X in simulation is not automatically picked up. I can assure you that real designs, with extensive validation can turn up odd bugs, or result in divergent errata - hence the 'err on the side of caution'. – Sean Houlihane Mar 16 '18 at 19:22

Such an assignment is useful during simulation, to make the waveform plots a little clearer.

Most synthesis tools will simply ignore any assignment to x. YMMV.

Assigning z to an external pin can be used to denote a tristate driver, but most FPGAs have limited, if any, support for internal tristate buses.

• Which synthesis tools will ignore assignments to 'x? For 'z modern FPGAs generally do not have internal tristate buses as you say, but the tools generally still support tristate bus models and will synthesize them to multiplexers. – pc3e Mar 16 '18 at 16:10
• @pc3e: All of them, as far as I know. Do you know of any that don't? – Dave Tweed Mar 16 '18 at 16:16
• All of them, as far as I know ;) See my answer. What tools are you using? – pc3e Mar 16 '18 at 16:19
• @pc3e: Your answer is talking about simulation, which I covered in my very first sentence. – Dave Tweed Mar 16 '18 at 16:22
• I am refering to Synopsys Design Compiler, Altera Quartus and Xilinx Vivado, which are all synthesis tools. – pc3e Mar 16 '18 at 16:53

The tool support for 'x as don't care seems to be pretty good. DC supports it, so does Intel FPGA (Altera) and Xilinx tools.

I think it is generally a good idea. Typically, and for your example, 'x propagation in simulation should not happen, because other logic should not care what the value of c is under the conditions that write 'x. (Otherwise it isn't "don't care", is it?) In fact, using 'x when you believe the value doesn't matter can help identify bugs.

However, there are cases where it can cause trouble. For example, serial transceiver protocols often use self-synchronizing scramblers, which would break down in simulation if some of the bits in the input data is 'x, even if you don't care what those bits end up as in the receiver, even if it works fine in hardware.

There is nothing as X for synthesis. It is mainly used for simulation to catch any data line related issues.