Assume there exists a 1 bit data output port and a 1 bit dataValid output port for a module. Is it OK to assign 1'dx to the data output when dataValid is assigned 0? Will this create synthesis issues?
EDIT: X optimizations seem to happen in both Synopsys DC and Cadence RC. Consider this code (a and b are 1-bit inputs and c is a 1-bit output).
always_comb if ( !a && !b ) c= 0; else if ( a && !b ) c = 1; else if ( !a && b ) c = 1; else c = 1'dx; // Don't care about this value.
gives an OR gate which is an optimized solution as opposed to an XOR which would have been inferred if c were set as 1'd0. This is a simple example but it seems to prove that synthesis tools do perform X optimization. Considering nasty X propagation bugs and verification troubles, are X assignments worth the saved area?