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There is a classic 6T SRAM cell (image from wikipedia):

SRAM cell (wiki, PD File:SRAM_Cell_(6_Transistors).svg)

It looks like (two inverters in opposite directions and interconnected in and out) and works like some flip-flop.

But what kind of flipflop is closest to such SRAM cell? I mean, is it latch or flipflop? Is it SR- or JK- or D- or T-latch/flipflop? It it NOR- or NAND- or Gate- latch?

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If I had to make a decision, I would say it looks closest to a D-latch. The problem is that a SRAM cell is not really analogous to a particular type of static CMOS storage because of the way it operates.

There's a few differences that make SRAM quite different:

  1. Transistor sizes determine if the cell will work at all. Most static CMOS logic will come to the right answer regardless of the relative transistor sizes, but the ratios of (M1,M3) to (M2,M4) to (M5,M6) need to be carefully selected to ensure that the cell is writable and readable.
  2. There is no specific input or output terminal (no D, CLK, or Q pins).
  3. A SRAM cell requires substantial support circuitry to function. The word-lines and bit-lines must be driven and read correctly in order for data to be reliably stored and retrieved.
  4. A SRAM cell is designed to operate in an array. While nothing precludes most latches or flip-flops from being used in an array, it would be unreasonable to use a SRAM bit as a stand-alone single bit storage.

While there are similarities, SRAM and DRAM don't share a close relationship between any of the stand-alone single-bit storage cells.

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A typical SRAM uses a trick I call "resistor priority logic", even though it actually uses variable-sized transistors rather than resistors. A "normal" latch design would use transistors to control whether the input to one of the inverters should be driven by the holding latch or by the signal to be latched. This would allow a new value to be latched without generating any bus conflicts, but would require more transistors per memory cell. It's cheaper and easier to make sure that when writing a memory cell, the bus is driven hard enough that--even with the memory cell transistors trying to drive the bus to the opposite state--the bus transistors will overpower the transistors in the memory cell, but when reading, the memory transistors are large enough to drive the bus when nothing else is doing so. This type of trick requires some care in manufacture, to achieve the optimal balance between having the memory-cell transistors large enough to drive the bus at reasonable speed, but small enough that the bus drive transistors can overpower them without wasting too much energy. The amount of tweaking necessary to make this type of logic work efficiently is such that it isn't used much. On the other hand, RAM is sufficiently common that it's worthwhile for chip manufacturers to refine their process especially for it.

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  • \$\begingroup\$ An excellent explanation written with much understanding... I would add another even more sophisticated explanation. Shortly after the beginning of the transition (switching), the memory cell acts as a kind of a a negative resistor that already "helps" the writing circuit... \$\endgroup\$ – Circuit fantasist Jan 31 '15 at 7:03
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It's closest to an SR latch, but instead of being made with NAND/NOR it's made with two inverters.
The transistors M5 and M6 have higher drive than the output of inverters (M1/M2 and M3/M4) overriding the output 1 or 0 and setting a new one, which is then reinforced by the M1/M2 M3/M4 "latch".
See the answers here and here also.

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