In design, an external clock pin triggers a flip-flop, where the output goes to an external data pin.
Using Xilinx ISE, how can I specify a timing constraint, so the output should be held for some short time after the rising edge of the external clock?
I have looked in the Xilinx Constraints Guide, and it has:
OFFSET = OUT {time_after} AFTER {clock};
But this constraint allows output data to change immediately after the clock, thus with a minimum clock to output time of 0 ps, thereby specifying a duration of {time_after} where the output is undefined.
In compare, for inputs, the constrains is:
OFFSET = IN {time_before} VALID {time_valid} BEFORE {clock};
So here the duration of the defined data can be specified to {time_valid}, but with an independent start time given as {time_before}.
However, it appears that output timing constraints does not have the same flexibility, or I have not found it ☺