As far as I am aware, this is an incorrect implementation of an AND gate, as when out is logic high, the two N-type FET transistors will go to an open state, leaving it floating. I am doubting my understanding, can someone clarify?

AND gate from https://www.cs.uaf.edu/2011/fall/cs441/lecture/09_05_semiconductors.html

From Building Logic Gates from Silicon (CS 441 Lecture, Dr. Lawlor).

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    \$\begingroup\$ +1 for spotting that indeed this is an incorrect implementation on a University Lecture webpage ! Always check that it makes sense. Obviously the person who made the Lecture didn't :-( \$\endgroup\$ – Bimpelrekkie Apr 2 '16 at 17:38
  • \$\begingroup\$ For those who are wondering why the linked website doesn´t show the AND-Gate but instead a NAND-Gate from Wikipedia - they´ve replaced the image. \$\endgroup\$ – mondlos Nov 15 '18 at 17:16

Let us analyze your circuit.

When both inputs are low, the PMOS are on, the NMOS are off, the out is tied low by the PMOS.

When both inputs are high, the NMOS are on, the PMOS are off, the out is tied high by the NMOS.

When one input is high and one is low, e.g. A=1, B=0, the rightmost PMOS is on, while the leftmost is off, the top NMOS is on but the bottom NMOS is off, so the output is tied low by the rightmost PMOS and no transistor can try to tie it high, so the circuit is still working.

If you work out the truth table you will see that the circuit is indeed an AND port.

The circuit has a problem though: it employs PMOS for the low side, and NMOS for the high side. If you use transistors with an high threshold voltage when you try to turn them on, with Vgs=0, they are not really on, they are in subthreshold region and conduct just a bit more than a transistor with a negative (wrt to the usual gate voltage you would apply to it depending on the MOS polarity) gate to source voltage.

The problem can be solved by using devices with a negative threshold voltage, so that Vgs=0 is enough to turn them fully on.

Please note that statically, having transistors in ST region might not be a big problem, but they can carry a lower than usual current, which results in slower transients of the output, especially with capacitive loads.

  • \$\begingroup\$ Thanks, I was not aware that such negative threshold devices existed, are they common? \$\endgroup\$ – jayjay Apr 2 '16 at 15:35
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    \$\begingroup\$ have a look at depletion mode transistors: in such devices the channel is already formed with no Vgs and you have to apply one to remove the channel and turn the device off. They are not used in CMOS logic though, an AND gate would be done with a NAND and a NOT gate. \$\endgroup\$ – Vladimir Cravero Apr 2 '16 at 15:41
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    \$\begingroup\$ Depletion type devices exist, you have to apply a negative voltage to these to switch them off. They are used for some analog applications. But no one uses them for logic cells like AND gates. Today 99.999% of logic ICs use Enhancement type MOSFETs. \$\endgroup\$ – Bimpelrekkie Apr 2 '16 at 15:41
  • \$\begingroup\$ This circuit is indeed an AND gate, but not a very good one. For robust logic circuits (containing multiple gates), you need logic level restoration -- basically gain -- where the output levels become very close to the logic rails even when the inputs are not so close. in this circuit, the gain is less than 1.0, and so you can't chain an arbitrary number of gates together. If you use depletion devices, the upper NMOS will leak some current (even with the inputs low), so the output low-level voltage won't be quite equal to the rail. \$\endgroup\$ – jp314 Apr 2 '16 at 20:15

I think you should ignore this circuit as it makes little sense. I have seen plenty of designs of AND gates from various IC manufacturers and none of them use this schematic.

Why ? Because the PMOS and NMOS transistors are exchanged for some strange reason.

This is what a proper AND gate looks like:

enter image description here

Note how all PMOS fets are connected at the upper side of the circuit, connecting to VDD, not ground / VSS-.

Like Vladimir writes in his answer, it will perform some function. But I would not remeber this as the proper implementation of an AND gate !

In the lecture there's a drawing of a layout next to the circuit. In it the Nwell is connected to VSS-, that is just plain WRONG The Nwell must be positive biased so that the Nwell-Substrate diode is in reverse mode.

In my opinion this Lecture was made by someone who does not fully understand the subject, which is dissapointing. I think this person assumes that a PMOS is always fully ON whenever the gate is at a low voltage (and NMOS with a high voltage). But this is not the case, the behaviour is more complex then that as any Analog CMOS designer can tell you.

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    \$\begingroup\$ +1. The idea basically is that op circuit sucks, and probably dissipates static power, which is unfortunate at the very least. \$\endgroup\$ – Vladimir Cravero Apr 2 '16 at 15:44
  • \$\begingroup\$ It is a shame that it is used in a lecture, confusing students :-( \$\endgroup\$ – Bimpelrekkie Apr 2 '16 at 15:47

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